J.L. Burns

799 citations

28 papers · 552 indexed · h-index 13

Impact in

Hardware and Architecture top 5%
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 10%
- Low-power high-performance VLSI design
- Advancements in Semiconductor Devices and Circuit Design
- VLSI and FPGA Design Techniques
- Semiconductor materials and devices
- Radio Frequency Integrated Circuit Design

Papers in

Hardware and Architecture 14
- VLSI and Analog Circuit Testing 8
- Parallel Computing and Optimization Techniques 5
- Embedded Systems Design Techniques 4
Electrical and Electronic Engineering 28
- Low-power high-performance VLSI design 17
- VLSI and FPGA Design Techniques 10
- Advancements in Semiconductor Devices and Circuit Design 6
- Semiconductor materials and devices 5
- 3D IC and TSV technologies 4

Co-authors: Richard B. Brown Kevin Nowka Tuyet Nguyen Rahul Rao Hùng Ngô Gary D. Carpenter Bishop Brock Eric MacDonald
Journals: IEEE Journal of Solid-State Circuits (3 papers)IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2 papers)Computer-Aided Design (1 paper)2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) (1 paper)International Conference on Computer Aided Design (1 paper)
Partner nations: United States Israel

In The Last Decade

J.L. Burns

27 papers receiving 514 citations

Peers

Countries citing papers authored by J.L. Burns

Since Specialization

Citations

This map shows the geographic impact of J.L. Burns's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J.L. Burns with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J.L. Burns more than expected).

Fields of papers citing papers by J.L. Burns

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J.L. Burns. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J.L. Burns. The network helps show where J.L. Burns may publish in the future.

Co-authors

The 25 scholars most cited alongside J.L. Burns, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with J.L. Burns Line = papers co-authored together J.L. Burns links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work
1	System Performance: From Enterprise to AI Mariana de Paula Silva, L. Chang, Gustavo Tèllez, Cheri Sugal, J.L. Burns	2018	1
2	Technology trends and implications on SoC design J.L. Burns	2011	1
3	Resonant clocking using distributed parasitic capacitance IEEE Journal of Solid-State Circuits ·Alan J. Drake, Kevin Nowka, Tuyet Nguyen, J.L. Burns, Richard B. Brown	2004	83
4	Resonant clocking using distributed parasitic capacitance Alan J. Drake, Kevin Nowka, Tuyet Nguyen, J.L. Burns, Richard B. Brown	2004	5
5	Circuit techniques for gate and sub-threshold leakage minimization in future CMOS technologies Rahul Rao, J.L. Burns, Richard B. Brown	2004	12
6	A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits International Conference on Computer Aided Design ·Rahul Rao, Frank Liu, J.L. Burns, Richard B. Brown	2003	27
7	A semi-custom voltage-island technique and its application to high-speed serial links [CMOS active power reduction] K. Havrylenko, J.L. Burns, Seung-Moon Yoo, Ivan Vo, Tubey R. J	2003	1
8	Efficient techniques for gate leakage estimation Rahul Rao, J.L. Burns, Anirudh Devgan, Richard B. Brown	2003	46
9	Efficient techniques for gate leakage estimation Rahul Rao, J.L. Burns, Anirudh Devgan, Richard B. Brown	2003	2
10	A semi-custom voltage-island technique and its application to high-speed serial links Kouzou Ohara, J.L. Burns, Seung-Moon Yoo, Ivan Vo, Tubey R. J	2003	1
11	A heuristic to determine low leakage sleep state vectors for CMOS combinational circuits Rahul Rao, 贺心源, J.L. Burns, Richard B. Brown	2003	18
12	The effect of wire length minimization on yield Ирина Алексеевна Пинясова, Israel Koren, J.L. Burns	2002	3
13	A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling IEEE Journal of Solid-State Circuits ·Kevin Nowka, Gary D. Carpenter, Eric MacDonald, Hùng Ngô, Bishop Brock, Hanauer Stephen H., Tuyet Nguyen, J.L. Burns	2002	157
14	Performance driven synthesis for pass-transistor logic Y Aguilera, Malay Ganai, A. Aziz, J.L. Burns	1999	14
15	C5M-a control-logic layout synthesis system for high-performance microprocessors IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·J.L. Burns, Trent A. Pinto	1998	20
16	C5M---a control logic layout synthesis system for high-performance microprocessors J.L. Burns, Trent A. Pinto	1997	4
17	Techniques for multilayer channel routing Computer-Aided Design ·Ma. Eugenia Cisneros López, J.L. Burns, Francesco Romeo, Alberto Sangiovanni‐Vincentelli, Kartikeya Mayaram, Longxi Li, Maria Eduarda Nunes Guimarães Pommer	1988	1
18	Techniques for multilayer channel routing IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Ma. Eugenia Cisneros López, J.L. Burns, Francesco Romeo, Alberto Sangiovanni‐Vincentelli, Kartikeya Mayaram, Srinivas Devadas, H.-K.T. Ma	1988	19
19	Chameleon: A New Multi-Layer Channel Router Ma. Eugenia Cisneros López, J.L. Burns, Srinivas Devadas, Md. Abdullah Rumman, Amable Ambrós Dra.C. Zoraida, Francesco Romeo, Alberto Sangiovanni‐Vincentelli	1986	29
20	Computer-aided prediction of high-frequency performance limits in silicon bipolar integrated circuits J.L. Burns, J. Choma	1982	1

About J.L. Burns

J.L. Burns is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Biomedical Engineering, Computer Networks and Communications and Infectious Diseases, having authored 28 papers that have together received 552 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (17 papers), VLSI and FPGA Design Techniques (10 papers), VLSI and Analog Circuit Testing (8 papers), Advancements in Semiconductor Devices and Circuit Design (6 papers), Parallel Computing and Optimization Techniques (5 papers), Semiconductor materials and devices (5 papers), Embedded Systems Design Techniques (4 papers) and 3D IC and TSV technologies (4 papers). The work is most often cited by research in Hardware and Architecture (238 citations), Electrical and Electronic Engineering (512 citations), Computer Networks and Communications (85 citations), Computational Theory and Mathematics (35 citations) and Software (6 citations). J.L. Burns has collaborated with scholars based in United States and Israel. Frequent co-authors include Richard B. Brown, Kevin Nowka, Tuyet Nguyen, Rahul Rao, Hùng Ngô, Gary D. Carpenter, Bishop Brock, Eric MacDonald, Alan J. Drake and Anirudh Devgan. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Computer-Aided Design, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) and International Conference on Computer Aided Design.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact