C. N. Sze

757 total citations
31 papers, 584 citations indexed

About

C. N. Sze is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, C. N. Sze has authored 31 papers receiving a total of 584 indexed citations (citations by other indexed papers that have themselves been cited), including 30 papers in Electrical and Electronic Engineering, 27 papers in Hardware and Architecture and 4 papers in Computer Networks and Communications. Recurrent topics in C. N. Sze's work include VLSI and FPGA Design Techniques (29 papers), Low-power high-performance VLSI design (24 papers) and VLSI and Analog Circuit Testing (19 papers). C. N. Sze is often cited by papers focused on VLSI and FPGA Design Techniques (29 papers), Low-power high-performance VLSI design (24 papers) and VLSI and Analog Circuit Testing (19 papers). C. N. Sze collaborates with scholars based in United States, China and Taiwan. C. N. Sze's co-authors include Charles J. Alpert, Jiang Hu, Gi-Joon Nam, Weiping Shi, Zhuo Li, P.J. Restle, Jiang Hu, Sachin S. Sapatnekar, Michael D. Moffitt and Stephen T. Quay and has published in prestigious journals such as Proceedings of the IEEE, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and International Conference on Computer Aided Design.

In The Last Decade

C. N. Sze

31 papers receiving 547 citations

Peers

C. N. Sze
Kwok-Shing Leung United States
Stephen T. Quay United States
M.A.B. Jackson United States
Tianming Kong United States
K.S. Khouri United States
Aristides Efthymiou United Kingdom
K. Chaudhary United States
R. M. Averill United States
Kee Sup Kim United States
T. McPherson United States
Kwok-Shing Leung United States
C. N. Sze
Citations per year, relative to C. N. Sze C. N. Sze (= 1×) peers Kwok-Shing Leung

Countries citing papers authored by C. N. Sze

Since Specialization
Citations

This map shows the geographic impact of C. N. Sze's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by C. N. Sze with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites C. N. Sze more than expected).

Fields of papers citing papers by C. N. Sze

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by C. N. Sze. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by C. N. Sze. The network helps show where C. N. Sze may publish in the future.

Co-authorship network of co-authors of C. N. Sze

This figure shows the co-authorship network connecting the top 25 collaborators of C. N. Sze. A scholar is included among the top collaborators of C. N. Sze based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with C. N. Sze. C. N. Sze is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Alpert, Charles J., et al.. (2012). Placement. 283–290. 18 indexed citations
2.
Moffitt, Michael D. & C. N. Sze. (2011). Wire synthesizable global routing for timing closure. Asia and South Pacific Design Automation Conference. 545–550. 6 indexed citations
3.
Tian, Haitong, et al.. (2011). Grid-to-ports clock routing for high performance microprocessor designs. 21–28. 1 indexed citations
4.
Zhou, Qiang, et al.. (2011). Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. 199–204. 8 indexed citations
5.
Moffitt, Michael D. & C. N. Sze. (2011). Wire synthesizable global routing for timing closure. 27. 545–550. 5 indexed citations
6.
Sze, C. N.. (2010). ISPD 2010 high performance clock network synthesis contest. 143–143. 72 indexed citations
7.
Luo, Tao, David Papa, Zhuo Li, et al.. (2008). Pyramids: an efficient computational geometry-based approach for timing-driven placement. International Conference on Computer Aided Design. 204–211. 8 indexed citations
8.
Papa, David, Tao Luo, Michael D. Moffitt, et al.. (2008). RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27(12). 2156–2168. 19 indexed citations
9.
Sze, C. N., Charles J. Alpert, Jiang Hu, & Weiping Shi. (2007). Path-Based Buffer Insertion. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26(7). 1346–1355. 5 indexed citations
10.
Alpert, Charles J., Zhuo Li, Gi-Joon Nam, et al.. (2007). Techniques for Fast Physical Synthesis. Proceedings of the IEEE. 95(3). 573–599. 64 indexed citations
11.
Alpert, Charles J., Jiang Hu, Sachin S. Sapatnekar, & C. N. Sze. (2006). Accurate estimation of global buffer delay within a floorplan. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 25(6). 1140–1145. 28 indexed citations
12.
Hu, Shiyan, Charles J. Alpert, Jiang Hu, et al.. (2006). Fast algorithms for slew constrained minimum cost buffering. 308–308. 21 indexed citations
13.
Alpert, Charles J., Andrew B. Kahng, C. N. Sze, & Qinke Wang. (2006). Timing-driven Steiner trees are (practically) free. 389–389. 21 indexed citations
14.
Li, Zhuo, C. N. Sze, Charles J. Alpert, Jiang Hu, & Weiping Shi. (2005). Making fast buffer insertion even faster via approximation techniques. 13–18 Vol. 1. 11 indexed citations
15.
Alpert, Charles J., Jiang Hu, Sachin S. Sapatnekar, & C. N. Sze. (2005). Accurate estimation of global buffer delay within a floorplan. 21. 706–711. 19 indexed citations
16.
Sze, C. N., Jiang Hu, & Charles J. Alpert. (2004). A place and route aware buffered Steiner tree construction. Asia and South Pacific Design Automation Conference. 355–360. 2 indexed citations
17.
Alpert, Charles J., et al.. (2004). Porosity-Aware Buffered Steiner Tree Construction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 23(4). 517–526. 10 indexed citations
18.
Sze, C. N. & Ting-Chi Wang. (2003). Performance-driven multi-level clustering for combinational circuits. 729–729. 4 indexed citations
19.
Lui, John C. S., et al.. (2003). An optimized routing scheme and a channel reservation strategy for a low Earth orbit satellite system. 5. 2870–2874. 3 indexed citations
20.
Wu, Yu‐Liang, C. N. Sze, Ray C. C. Cheung, & Heliang Fan. (2002). On improved graph-based alternative wiring scheme for multi-level logic optimization. 2. 654–657. 6 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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