N. Jarwala
- Hardware and Architecture top 5%
- Electrical and Electronic Engineering
- Control and Systems Engineering
- Computer Networks and Communications
- Computational Theory and Mathematics
- Topics
- VLSI and Analog Circuit Testing (11 papers)Engineering and Test Systems (6 papers)Integrated Circuits and Semiconductor Failure Analysis (5 papers)
- Partner nations
- United States
In The Last Decade
N. Jarwala
11 papers receiving 114 citations
Peers
Comparison fields: 5 of 13
- Hardware and Architecture 119
- Electrical and Electronic Engineering 108
- Control and Systems Engineering 21
- Computer Networks and Communications 17
- Computational Theory and Mathematics 7
Countries citing papers authored by N. Jarwala
This map shows the geographic impact of N. Jarwala's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by N. Jarwala with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites N. Jarwala more than expected).
Fields of papers citing papers by N. Jarwala
This network shows the impact of papers produced by N. Jarwala. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by N. Jarwala. The network helps show where N. Jarwala may publish in the future.
Co-authorship network of co-authors of N. Jarwala
This figure shows the co-authorship network connecting the top 25 collaborators of N. Jarwala. A scholar is included among the top collaborators of N. Jarwala based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with N. Jarwala. N. Jarwala is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 0 | |
| 2 | 5 | |
| 3 | 25 | |
| 4 | 1 | |
| 5 | 47 | |
| 6 | 10 | |
| 7 | 3 | |
| 8 | 5 | |
| 9 | 11 | |
| 10 | 1 | |
| 11 | 18 | |
| 12 | 1 |
About N. Jarwala
N. Jarwala is a scholar working on Hardware and Architecture, Control and Systems Engineering and Electrical and Electronic Engineering, having authored 12 papers that have together received 127 indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (11 papers), Engineering and Test Systems (6 papers) and Integrated Circuits and Semiconductor Failure Analysis (5 papers). The work is most often cited by research in Hardware and Architecture (119 citations), Electrical and Electronic Engineering (108 citations) and Software (6 citations). N. Jarwala has collaborated with scholars based in United States. Frequent co-authors include Dhiraj K. Pradhan, Benoit Nadeau-Dostie, Y. Zorian and Rodham E. Tulloss. Their work appears in journals such as Computer, IEEE Transactions on Computers and Journal of Electronic Testing.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.