Anuja Sehgal

401 total citations
22 papers, 306 citations indexed

About

Anuja Sehgal is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Control and Systems Engineering. According to data from OpenAlex, Anuja Sehgal has authored 22 papers receiving a total of 306 indexed citations (citations by other indexed papers that have themselves been cited), including 21 papers in Hardware and Architecture, 21 papers in Electrical and Electronic Engineering and 4 papers in Control and Systems Engineering. Recurrent topics in Anuja Sehgal's work include VLSI and Analog Circuit Testing (21 papers), Integrated Circuits and Semiconductor Failure Analysis (18 papers) and VLSI and FPGA Design Techniques (12 papers). Anuja Sehgal is often cited by papers focused on VLSI and Analog Circuit Testing (21 papers), Integrated Circuits and Semiconductor Failure Analysis (18 papers) and VLSI and FPGA Design Techniques (12 papers). Anuja Sehgal collaborates with scholars based in United States, Netherlands and India. Anuja Sehgal's co-authors include Krishnendu Chakrabarty, Erik Jan Marinissen, V. Iyengar, S.K. Goel, Sandeep Goel, Jeff Rearick, Sule Ozev, Vikram Iyengar, Peilin Song and K.A. Jenkins and has published in prestigious journals such as IEEE Transactions on Computers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and ACM Transactions on Design Automation of Electronic Systems.

In The Last Decade

Anuja Sehgal

22 papers receiving 288 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Anuja Sehgal United States 12 285 282 30 28 11 22 306
Urban Ingelsson Sweden 10 285 1.0× 276 1.0× 27 0.9× 43 1.5× 10 0.9× 25 307
Teresa McLaurin United States 11 275 1.0× 258 0.9× 32 1.1× 31 1.1× 7 0.6× 24 296
Rubin Parekhji India 12 293 1.0× 312 1.1× 29 1.0× 33 1.2× 9 0.8× 65 332
A.S.M. Hassan Canada 5 309 1.1× 320 1.1× 28 0.9× 40 1.4× 4 0.4× 6 340
G. Hetherington United States 6 451 1.6× 447 1.6× 20 0.7× 65 2.3× 7 0.6× 8 466
Vivek Chickermane United States 15 573 2.0× 597 2.1× 14 0.5× 50 1.8× 12 1.1× 43 623
G. Gronthoud Netherlands 12 429 1.5× 447 1.6× 11 0.4× 35 1.3× 17 1.5× 26 470
E. Volkerink United States 10 390 1.4× 381 1.4× 14 0.5× 70 2.5× 4 0.4× 12 402
Ho Fai Ko Canada 11 403 1.4× 363 1.3× 25 0.8× 13 0.5× 5 0.5× 23 414
V.A. Vardanian United States 12 320 1.1× 336 1.2× 29 1.0× 21 0.8× 2 0.2× 27 359

Countries citing papers authored by Anuja Sehgal

Since Specialization
Citations

This map shows the geographic impact of Anuja Sehgal's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Anuja Sehgal with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Anuja Sehgal more than expected).

Fields of papers citing papers by Anuja Sehgal

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Anuja Sehgal. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Anuja Sehgal. The network helps show where Anuja Sehgal may publish in the future.

Co-authorship network of co-authors of Anuja Sehgal

This figure shows the co-authorship network connecting the top 25 collaborators of Anuja Sehgal. A scholar is included among the top collaborators of Anuja Sehgal based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Anuja Sehgal. Anuja Sehgal is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Sehgal, Anuja, et al.. (2022). Technical Resilience in Intrapreneurs for Product Innovations : An Exploratory Study. Prabandhan Indian Journal of Management. 15(10). 28–28. 1 indexed citations
2.
Sinanoglu, Ozgur, et al.. (2009). Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Design & Test of Computers. 26(3). 25–37. 16 indexed citations
3.
Sehgal, Anuja, et al.. (2008). Test Access Mechanism for Multiple Identical Cores. 1–10. 42 indexed citations
4.
Sehgal, Anuja, et al.. (2008). Power-aware SoC test planning for effective utilization of port-scalable testers. ACM Transactions on Design Automation of Electronic Systems. 13(3). 1–19. 3 indexed citations
5.
Goel, Sandeep, Erik Jan Marinissen, Anuja Sehgal, & Krishnendu Chakrabarty. (2008). Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. IEEE Transactions on Computers. 58(3). 409–423. 33 indexed citations
6.
Sehgal, Anuja & Krishnendu Chakrabarty. (2007). Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. IEEE Transactions on Computers. 56(1). 120–133. 5 indexed citations
7.
Sehgal, Anuja, et al.. (2007). Test cost reduction for the AMD™ Athlon processor using test partitioning. 13. 1–10. 11 indexed citations
8.
Sehgal, Anuja, Sule Ozev, & Krishnendu Chakrabarty. (2006). A flexible design methodology for analog test wrappers in mixed-signal SOCs. 28. 137–142. 1 indexed citations
9.
Sehgal, Anuja, Sule Ozev, & Krishnendu Chakrabarty. (2006). Test infrastructure design for mixed-signal SOCs with wrapped analog cores. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 14(3). 292–304. 12 indexed citations
10.
Sehgal, Anuja, Peilin Song, & K.A. Jenkins. (2006). On-chip Real-Time Power Supply Noise Detector. 380–383. 19 indexed citations
11.
Sehgal, Anuja & Krishnendu Chakrabarty. (2006). Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. IEEE Transactions on Computers. 56(1). 120–133. 6 indexed citations
12.
Sehgal, Anuja, S.K. Goel, Erik Jan Marinissen, & Krishnendu Chakrabarty. (2006). Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips. 18. 1–6. 12 indexed citations
13.
Sehgal, Anuja & Krishnendu Chakrabarty. (2005). Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs. 88–93. 5 indexed citations
14.
Sehgal, Anuja, Ankit Dubey, Erik Jan Marinissen, et al.. (2005). Redundancy modelling and array yield analysis for repairable embedded memories. IEE Proceedings - Computers and Digital Techniques. 152(1). 97–97. 14 indexed citations
15.
Sehgal, Anuja, S.K. Goel, Erik Jan Marinissen, & Krishnendu Chakrabarty. (2005). IEEE P1500-compliant test wrapper design for hierarchical cores. 1203–1212. 26 indexed citations
16.
Sehgal, Anuja & Krishnendu Chakrabarty. (2004). Efficient modular testing of SoCs using dual-speed TAM architectures. Design, Automation, and Test in Europe. 1. 10422. 12 indexed citations
17.
Sehgal, Anuja, V. Iyengar, & Krishnendu Chakrabarty. (2004). SOC test planning using virtual test access architectures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 12(12). 1263–1276. 37 indexed citations
18.
Sehgal, Anuja, Sule Ozev, & Krishnendu Chakrabarty. (2003). TAM Optimization for Mixed-Signal SOCs using Analog Test Wrappers. International Conference on Computer Aided Design. 95–99. 8 indexed citations
19.
Sehgal, Anuja, et al.. (2003). Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. 2 indexed citations
20.
Sehgal, Anuja, et al.. (2003). Test cost reduction for SOCs using virtual TAMs and lagrange multipliers. 738–743. 20 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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