Anuja Sehgal
- Hardware and Architecture top 2%
- Electrical and Electronic Engineering
- Computer Networks and Communications
- Control and Systems Engineering
- Biomedical Engineering
- Co-authors
- Krishnendu ChakrabartyErik Jan MarinissenV. IyengarS.K. GoelSandeep GoelJeff RearickSule OzevVikram Iyengar
- Topics
- VLSI and Analog Circuit Testing (21 papers)Integrated Circuits and Semiconductor Failure Analysis (18 papers)VLSI and FPGA Design Techniques (12 papers)
- Journals
- IEEE Transactions on ComputersIEEE Transactions on Very Large Scale Integration (VLSI) SystemsACM Transactions on Design Automation of Electronic Systems
- Partner nations
- United StatesNetherlandsIndia
In The Last Decade
Anuja Sehgal
22 papers receiving 288 citations
Peers
Comparison fields: 5 of 14
- Hardware and Architecture 285
- Electrical and Electronic Engineering 282
- Computer Networks and Communications 30
- Control and Systems Engineering 28
- Biomedical Engineering 11
Countries citing papers authored by Anuja Sehgal
This map shows the geographic impact of Anuja Sehgal's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Anuja Sehgal with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Anuja Sehgal more than expected).
Fields of papers citing papers by Anuja Sehgal
This network shows the impact of papers produced by Anuja Sehgal. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Anuja Sehgal. The network helps show where Anuja Sehgal may publish in the future.
Co-authorship network of co-authors of Anuja Sehgal
This figure shows the co-authorship network connecting the top 25 collaborators of Anuja Sehgal. A scholar is included among the top collaborators of Anuja Sehgal based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Anuja Sehgal. Anuja Sehgal is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 1 | |
| 2 | 16 | |
| 3 | 42 | |
| 4 | 3 | |
| 5 | 33 | |
| 6 | 5 | |
| 7 | 11 | |
| 8 | 1 | |
| 9 | 12 | |
| 10 | 19 | |
| 11 | 6 | |
| 12 | 12 | |
| 13 | 5 | |
| 14 | 14 | |
| 15 | 26 | |
| 16 | 12 | |
| 17 | 37 | |
| 18 | 8 | |
| 19 | 2 | |
| 20 | 20 |
About Anuja Sehgal
Anuja Sehgal is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Control and Systems Engineering, having authored 22 papers that have together received 306 indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (21 papers), Integrated Circuits and Semiconductor Failure Analysis (18 papers) and VLSI and FPGA Design Techniques (12 papers). The work is most often cited by research in Hardware and Architecture (285 citations), Electrical and Electronic Engineering (282 citations) and Software (10 citations). Anuja Sehgal has collaborated with scholars based in United States, Netherlands and India. Frequent co-authors include Krishnendu Chakrabarty, Erik Jan Marinissen, V. Iyengar, S.K. Goel, Sandeep Goel, Jeff Rearick, Sule Ozev, Vikram Iyengar, Peilin Song and K.A. Jenkins. Their work appears in journals such as IEEE Transactions on Computers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and ACM Transactions on Design Automation of Electronic Systems.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.