Kanyu Cao

410 total citations
25 papers, 275 citations indexed

About

Kanyu Cao is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, Kanyu Cao has authored 25 papers receiving a total of 275 indexed citations (citations by other indexed papers that have themselves been cited), including 24 papers in Electrical and Electronic Engineering, 3 papers in Hardware and Architecture and 2 papers in Computer Networks and Communications. Recurrent topics in Kanyu Cao's work include Semiconductor materials and devices (22 papers), Advancements in Semiconductor Devices and Circuit Design (17 papers) and Integrated Circuits and Semiconductor Failure Analysis (7 papers). Kanyu Cao is often cited by papers focused on Semiconductor materials and devices (22 papers), Advancements in Semiconductor Devices and Circuit Design (17 papers) and Integrated Circuits and Semiconductor Failure Analysis (7 papers). Kanyu Cao collaborates with scholars based in China, United States and Hong Kong. Kanyu Cao's co-authors include Chenming Hu, Xiaodong Jin, Wei Liu, Pin Su, Bin Yu, S.K.H. Fung, Jessica Krick, Weidong Liu, Ru Huang and Mansun Chan and has published in prestigious journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters and IEEE Transactions on Magnetics.

In The Last Decade

Kanyu Cao

21 papers receiving 250 citations

Peers

Kanyu Cao
R. Mahnkopf Germany
I. Aller Germany
Shien-Yang Wu Taiwan
E. Worley United States
J.J. Liaw Taiwan
Shita Guo United States
Youngdon Choi South Korea
Behzad Ebrahimi Iran
Samuel Tang United States
Yasufumi Hino United States
R. Mahnkopf Germany
Kanyu Cao
Citations per year, relative to Kanyu Cao Kanyu Cao (= 1×) peers R. Mahnkopf

Countries citing papers authored by Kanyu Cao

Since Specialization
Citations

This map shows the geographic impact of Kanyu Cao's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kanyu Cao with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kanyu Cao more than expected).

Fields of papers citing papers by Kanyu Cao

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Kanyu Cao. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kanyu Cao. The network helps show where Kanyu Cao may publish in the future.

Co-authorship network of co-authors of Kanyu Cao

This figure shows the co-authorship network connecting the top 25 collaborators of Kanyu Cao. A scholar is included among the top collaborators of Kanyu Cao based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Kanyu Cao. Kanyu Cao is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
2.
Liu, Yong, Pengpeng Ren, Maokun Wu, et al.. (2024). Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node—Part I: Defect-Based Statistical Compact Model. IEEE Transactions on Electron Devices. 71(8). 4462–4468. 1 indexed citations
3.
Liu, Yong, Pengpeng Ren, Maokun Wu, et al.. (2024). Understanding Retention Time Distribution in Buried-Channel-Array-Transistors (BCAT) Under Sub-20-nm DRAM Node—Part II: PBTI Aging and Optimization. IEEE Transactions on Electron Devices. 71(8). 4469–4475. 3 indexed citations
4.
Ren, Pengpeng, Zixuan Sun, Jianping Wang, et al.. (2023). Double-sided Row Hammer Effect in Sub-20 nm DRAM: Physical Mechanism, Key Features and Mitigation. 1–10. 14 indexed citations
5.
Ren, Pengpeng, Lining Zhang, Xiong Li, et al.. (2022). Defect-Based Empirical Model for On-State Degradation in Sub-20-nm DRAM Periphery pFETs Under Arbitrary Condition. IEEE Transactions on Electron Devices. 69(12). 6669–6675. 2 indexed citations
6.
7.
Li, Huihui, et al.. (2021). 72 nm Pitch Hexagonal MTJ Array on DRAM Platform for High-Density MRAM. IEEE Transactions on Magnetics. 57(11). 1–6. 5 indexed citations
8.
Cao, Kanyu, et al.. (2021). Trap-Assisted Passing Word Line Leakage and Variable Retention Time in DRAM. 338–341. 10 indexed citations
9.
Su, Xingsong, et al.. (2021). High density V-GAA transistor structure array based on self-aligned double patterning. 1–3. 1 indexed citations
10.
11.
Cao, Kanyu, et al.. (2021). Saddle Fin Structure Effects on the DRAM Access Transistor Performance. 50–53. 3 indexed citations
12.
Zhang, Hongguang, Zhiqiang Zhang, Yanan Zhang, et al.. (2021). A Data Eye Width Improved and ODT PVT Tolerance Enhanced DDR4 SDRAM Using Fast Clock Gating and tADC Self-align. 171–174. 1 indexed citations
13.
Liu, Zhongming, et al.. (2021). Pitch Device Design in 10nm-Class DRAM Process through DTCO. 1–4. 2 indexed citations
14.
Cao, Kanyu, et al.. (2020). A DTCO approach on DRAM bit line capacitance and sensing margin improvement. 1–3. 2 indexed citations
15.
Cao, Kanyu, Huijuan Liu, Bo Wang, et al.. (2016). A high speed low power negative sensing architecture for 3D NAND Flash memory. 50. 1–3.
16.
Chan, Mansun, Xuemei Xi, Jin He, et al.. (2003). Practical compact modeling approaches and options for sub-0.1 μm CMOS technologies. Microelectronics Reliability. 43(3). 399–404. 2 indexed citations
17.
He, Jin, Xuemei Xi, Mansun Chan, et al.. (2003). A physics-based analytical surface potential and capacitance model of MOSFET's operation from accumulation to depletion region. Rare & Special e-Zone (The Hong Kong University of Science and Technology). 2(2003). 302–305. 2 indexed citations
18.
Jin, Xiaodong, Kanyu Cao, Jia-Jiunn Ou, et al.. (2002). An accurate non-quasistatic MOSFET model for simulation of RF and high speed circuits. 196–197. 4 indexed citations
19.
He, Jin, Xuemei Xi, Mansun Chan, et al.. (2002). Normalized mutual integral difference method to extract threshold voltage of MOSFETs. IEEE Electron Device Letters. 23(7). 428–430. 15 indexed citations
20.
Cao, Kanyu, Wei Liu, Xiaodong Jin, et al.. (2002). BSIM4 gate leakage model including source-drain partition. 815–818. 149 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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