J.P. Parkerson

576 citations

33 papers · 387 indexed · h-index 11

Impact in

Computational Theory and Mathematics top 5%
- Quantum-Dot Cellular Automata
Hardware and Architecture top 10%
- VLSI and Analog Circuit Testing

Papers in

Hardware and Architecture 3
- VLSI and Analog Circuit Testing 3
Electrical and Electronic Engineering 23
- Low-power high-performance VLSI design 8
- Advancements in Semiconductor Devices and Circuit Design 6
- Energy Harvesting in Wireless Networks 3
- Advanced MEMS and NEMS Technologies 3

Co-authors: P.K. Lala Dilip Vasudevan Jia Di Pinaki Chakraborty Nilanjan Banerjee L.W. Schaper Simon S. Ang W.D. Brown
Journals: International Journal of Satellite Communications and Networking (1 paper)ACM Transactions on Embedded Computing Systems (1 paper)IEEE Transactions on Instrumentation and Measurement (1 paper)IEEE Transactions on Advanced Packaging (1 paper)IEEE Transactions on Circuits and Systems I Regular Papers (1 paper)
Partner nations: United States

In The Last Decade

J.P. Parkerson

31 papers receiving 342 citations

Peers

Countries citing papers authored by J.P. Parkerson

Since Specialization

Citations

This map shows the geographic impact of J.P. Parkerson's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J.P. Parkerson with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J.P. Parkerson more than expected).

Fields of papers citing papers by J.P. Parkerson

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J.P. Parkerson. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J.P. Parkerson. The network helps show where J.P. Parkerson may publish in the future.

Co-authorship network

The 24 scholars most cited alongside J.P. Parkerson, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with J.P. Parkerson Line = papers co-authored together J.P. Parkerson links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work
1	Gesture Classification with Low-Cost Capacitive Sensor Array for Upper Extremity Rehabilitation Haoyan Liu, Enrique Sánchez, J.P. Parkerson, Alexander Nelson	2019	1
2	Perpetuu ACM Transactions on Embedded Computing Systems ·Afolabi Kotoye, María J Pérez-Ortega, Nilanjan Banerjee, J.P. Parkerson, Ryan Robucci, Chintan Patel	2015	1
3	Wearable multi-sensor gesture recognition for paralysis patients Alexander Nelson, Kevin Geyer, Prashanth S. Kumar, Johnny Cooper, J.D. Edwards, Nilanjan Banerjee, Sami Rollins, J.P. Parkerson, Vijay K. Varadan	2013	27
4	Information Rich GIS Dissemination in Disconnected Environments Transactions in GIS ·William Johnston, Nilanjan Banerjee, Jackson Cothren, J.P. Parkerson	2013	1
5	Adder designs using reversible logic gates WSEAS Transactions on Circuits and Systems archive ·P.K. Lala, J.P. Parkerson, Pinaki Chakraborty	2010	25
6	An Approach for Implementing State Machines with Online Testability VLSI design ·P.K. Lala, Brent DuBois, J.P. Parkerson	2010	1
7	Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding IEEE Transactions on Circuits and Systems I Regular Papers ·Dilip Vasudevan, P.K. Lala, J.P. Parkerson	2007	59
8	Intra-satellite networking International Journal of Satellite Communications and Networking ·J.P. Parkerson, Tomeka Caroll, Hend Zedan, Mirella Martinelli Magnoli, Marina Omar	2006	0
9	Reversible-Logic Design With Online Testability IEEE Transactions on Instrumentation and Measurement ·Dilip Vasudevan, P.K. Lala, Jia Di, J.P. Parkerson	2006	108
10	On self-healing digital system design Microelectronics Journal ·P.K. Lala, Pradeep Mishra, J.P. Parkerson	2005	14
11	Logic implementation using a reversible gate. Dilip Vasudevan, J.P. Parkerson, P.K. Lala	2004	1
12	Online testable reversible logic circuit design using NAND blocks Dilip Vasudevan, P.K. Lala, J.P. Parkerson	2004	28
13	Recent developments in photonic networking components for space applications Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·J.P. Parkerson, C. Caravano, IAN MAGALHÃES DE ANDRADE, F. O. Oyebamiji, Hend Zedan, Mirella Martinelli Magnoli	2003	2
14	Design considerations for using integrated passive components J.P. Parkerson, L.W. Schaper, Anthony Scaramozzi	2002	3
15	<title>Photonic packaging for space applications</title> Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE ·J.P. Parkerson, F. O. Oyebamiji, Mirella Martinelli Magnoli, Tony Hull	2002	2
16	Advanced interconnected mesh power system (IMPS) MCM topologies J.P. Parkerson, L.W. Schaper	2002	1
17	Electrical characterization of multilayered thin film integral passive devices I Putu Citra, Anthony Scaramozzi, J.P. Parkerson, チョウコハタケヤマ, Simon S. Ang	2002	6
18	Getting aggressive with passive devices IEEE Circuits and Devices Magazine ·Richard K. Ulrich, W.D. Brown, 王成明, Fred Barlow, Aicha Elshabini, Anthony Scaramozzi, Hameed A. Naseem, A. A. Yashina, J.P. Parkerson, チョウコハタケヤマ, I Putu Citra	2000	7
19	Modeling and electrical analysis of seamless high off-chip connectivity (SHOCC) interconnects IEEE Transactions on Advanced Packaging ·Ji Young Kim, L.W. Schaper, J.P. Parkerson, W.D. Brown, Simon S. Ang, Hameed A. Naseem	1999	20
20	a Signal Noise Comparison of the Interconnected Mesh Power System (imps) with a Standard Four-Layer Mcm Topology Michael D. Glover, J.P. Parkerson, L.W. Schaper	1996	1

About J.P. Parkerson

J.P. Parkerson is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Human-Computer Interaction, Artificial Intelligence and Software, having authored 33 papers that have together received 387 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (8 papers), Quantum Computing Algorithms and Architecture (7 papers), Advancements in Semiconductor Devices and Circuit Design (6 papers), Satellite Communication Systems (4 papers), Energy Harvesting in Wireless Networks (3 papers), VLSI and Analog Circuit Testing (3 papers), Spacecraft Design and Technology (3 papers) and Advanced MEMS and NEMS Technologies (3 papers). The work is most often cited by research in Computational Theory and Mathematics (138 citations), Hardware and Architecture (57 citations), Artificial Intelligence (183 citations), Electrical and Electronic Engineering (284 citations) and Human-Computer Interaction (15 citations). J.P. Parkerson has collaborated with scholars based in United States. Frequent co-authors include P.K. Lala, Dilip Vasudevan, Jia Di, Pinaki Chakraborty, Nilanjan Banerjee, L.W. Schaper, Simon S. Ang, W.D. Brown, Alexander Nelson and Hameed A. Naseem. Their work appears in journals such as International Journal of Satellite Communications and Networking, ACM Transactions on Embedded Computing Systems, IEEE Transactions on Instrumentation and Measurement, IEEE Transactions on Advanced Packaging and IEEE Transactions on Circuits and Systems I Regular Papers.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact