Chia-Chun Lin

440 citations

37 papers · 291 indexed · h-index 10

Co-authors: Niraj K. Jha Amlan Chakrabarti Chun-Yao Wang Yung‐Chih Chen Susmita Sur‐Kolay Yung‐Hsien Wu Chia‐Hsuan Chang Jia‐Rong Wu
Topics: Advanced Memory and Neural Computing (10 papers)Quantum Computing Algorithms and Architecture (8 papers)Semiconductor materials and devices (7 papers)
Cited by: Computational Theory and Mathematics Hardware and Architecture Artificial Intelligence
Journals: Sensors RSC Advances IEEE Electron Device Letters
Partner nations: Taiwan United States Japan

In The Last Decade

Chia-Chun Lin

34 papers receiving 277 citations

Peers

Countries citing papers authored by Chia-Chun Lin

Since Specialization

Citations

This map shows the geographic impact of Chia-Chun Lin's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Chia-Chun Lin with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Chia-Chun Lin more than expected).

Fields of papers citing papers by Chia-Chun Lin

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Chia-Chun Lin. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Chia-Chun Lin. The network helps show where Chia-Chun Lin may publish in the future.

Co-authorship network of co-authors of Chia-Chun Lin

This figure shows the co-authorship network connecting the top 25 collaborators of Chia-Chun Lin. A scholar is included among the top collaborators of Chia-Chun Lin based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Chia-Chun Lin. Chia-Chun Lin is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A Wearable Assistant Device for the Hearing Impaired to Recognize Emergency Vehicle Sirens with Edge Computing 2023 ·Sensors ·Chiun-Li Chin,Chia-Chun Lin,Jingwen Wang,(unknown),Yu‐Hsiang Chen,(unknown),Pei‐Chen Huang,Xin Zhu,(unknown),Shing-Hong Liu	5
2	LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach 2021 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),(unknown),(unknown),Chia-Chun Lin,Yung‐Chih Chen,Chun-Yao Wang	10
3	Majority Logic Circuit Minimization Using Node Addition and Removal 2021 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),Chia-Chun Lin,Yung‐Chih Chen,Chun-Yao Wang	2
4	Don’t Care Computation and De Morgan Transformation for Threshold Logic Network Optimization 2021 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Chia-Chun Lin,(unknown),(unknown),Yung‐Chih Chen,Chun-Yao Wang	2
5	Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model 2021 ·ACM Journal on Emerging Technologies in Computing Systems ·(unknown),(unknown),Chia-Chun Lin,Yung‐Chih Chen,Juinn-Dar Huang,Chun-Yao Wang	1
6	A New Necessary Condition for Threshold Function Identification 2020 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Chia-Chun Lin,(unknown),Yung‐Chih Chen,Chun-Yao Wang	6
7	A Convolutional Result Sharing Approach for Binarized Neural Network Inference 2020 ·(unknown),Chia-Chun Lin,Yi-Ting Lin,Yung‐Chih Chen,Chun-Yao Wang	6
8	LOOPLock: Logic Optimization-Based Cyclic Logic Locking 2019 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),Yung‐Chih Chen,(unknown),(unknown),Chia-Chun Lin,Chun-Yao Wang	10
9	A Glitch Key-Gate for Logic Locking 2019 ·(unknown),(unknown),Chia-Chun Lin,(unknown),Yung‐Chih Chen,Chun-Yao Wang	1
10	On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses 2018 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown),Chia-Chun Lin,(unknown),Yung‐Chih Chen,Chun-Yao Wang	23
11	Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments 2018 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),Chia-Chun Lin,Yung‐Chih Chen,(unknown),Chun-Yao Wang,Shigeru Yamashita	8
12	Efficient synthesis of approximate threshold logic circuits with an error rate guarantee 2018 ·(unknown),Chia-Chun Lin,(unknown),Yung‐Chih Chen,Chun-Yao Wang	9
13	In&Out: Restructuring for threshold logic network optimization 2017 ·Chia-Chun Lin,(unknown),Chun-Yao Wang,Yung‐Chih Chen	6
14	A Monitor System for Software Version Request in Offline Environments 2017 ·International Journal of Security and Its Applications ·(unknown),Chia-Chun Lin	1
15	QLib 2014 ·ACM Journal on Emerging Technologies in Computing Systems ·Chia-Chun Lin,Amlan Chakrabarti,Niraj K. Jha	21
16	FTQLS: Fault-Tolerant Quantum Logic Synthesis 2013 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Chia-Chun Lin,Amlan Chakrabarti,Niraj K. Jha	18
17	Optimized Quantum Gate Library for Various Physical Machine Descriptions 2013 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Chia-Chun Lin,Amlan Chakrabarti,Niraj K. Jha	19
18	Self-align nitride based logic NVM in 28nm high-k metal gate CMOS technology 2013 ·(unknown),(unknown),(unknown),Chia-Chun Lin,Ya‐Chin King,(unknown)	4
19	Integration of Amorphous $\hbox{Yb}_{2}\hbox{O}_{3}$ and Crystalline $\hbox{ZrTiO}_{4}$ as Gate Stack for Aggressively Scaled MOS Devices 2012 ·IEEE Electron Device Letters ·Yung‐Hsien Wu,(unknown),(unknown),(unknown),Chia-Chun Lin	9
20	Elbow Load with Various Forearm Positions During One-Handed Pushup Exercise 2002 ·International Journal of Sports Medicine ·(unknown),Chia-Chun Lin,You-Li Chou,(unknown),Fong‐Chin Su,(unknown)	13

About Chia-Chun Lin

Chia-Chun Lin is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computational Theory and Mathematics, having authored 37 papers that have together received 291 indexed citations. Recurring topics across this work include Advanced Memory and Neural Computing (10 papers), Quantum Computing Algorithms and Architecture (8 papers) and Semiconductor materials and devices (7 papers). The work is most often cited by research in Computational Theory and Mathematics (78 citations), Hardware and Architecture (31 citations) and Artificial Intelligence (128 citations). Chia-Chun Lin has collaborated with scholars based in Taiwan, United States and Japan. Frequent co-authors include Niraj K. Jha, Amlan Chakrabarti, Chun-Yao Wang, Yung‐Chih Chen, Susmita Sur‐Kolay, Yung‐Hsien Wu, Chia‐Hsuan Chang, Jia‐Rong Wu, Yi-Ting Lin and Yun‐Ju Lee. Their work appears in journals such as Sensors, RSC Advances and IEEE Electron Device Letters.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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