H. Sunami

686 citations

37 papers · 527 indexed · h-index 13

Electrical and Electronic Engineering top 10%
- Semiconductor materials and devices 25
- Advancements in Semiconductor Devices and Circuit Design 18
- Advanced Memory and Neural Computing 9
- Ferroelectric and Negative Capacitance Devices 7
- Low-power high-performance VLSI design 5
- Advancements in Photolithography Techniques 4
- Silicon and Solar Cell Technologies 4
- Thin-Film Transistor Technologies 4
Hardware and Architecture
Surfaces, Coatings and Films
Computer Graphics and Computer-Aided Design
Biomedical Engineering

Co-authors: N. Hashimoto K. Itoh T. Kure S. Asai T. Toyabe K. Yagi Mitsumasa Koyanagi J. Etoh
Cited by: Electrical and Electronic Engineering Hardware and Architecture Surfaces, Coatings and Films
Journals: IEEE Transactions on Electron Devices (8 papers)IEEE Electron Device Letters (4 papers)IEEE Journal of Solid-State Circuits (4 papers)
Partner nations: Japan United Kingdom United States

In The Last Decade

H. Sunami

36 papers receiving 510 citations

Peers

Countries citing papers authored by H. Sunami

Since Specialization

Citations

This map shows the geographic impact of H. Sunami's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by H. Sunami with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites H. Sunami more than expected).

Fields of papers citing papers by H. Sunami

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by H. Sunami. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by H. Sunami. The network helps show where H. Sunami may publish in the future.

Co-authorship network

The 25 scholars most cited alongside H. Sunami, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with H. Sunami Line = papers co-authored together H. Sunami links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

#	Work
1	A 3D integration scheme utilizing wireless interconnections for implementing hyper brains Akira Iwata,Mamoru Sasaki,Takamaro Kikkawa,Seiji Kameda,Hideyuki Ando,Pritesh R Jain,Arndt Franke,H. Sunami	2005	24
2	A new stacked capacitor DRAM cell characterized by a storage capacitor on a bit-line structure S. Kimura,Y. Kawamoto,T. Kure,Norio Hasegawa,J. Etoh,Masakazu Aoki,Eiji Takeda,H. Sunami,K. Itoh	2003	3
3	A diagonal active-area stacked capacitor DRAM cell with storage capacitor on bit line IEEE Transactions on Electron Devices ·S. Kimura,Y. Kawamoto,T. Kure,Norio Hasegawa,T. Kisu,J. Etoh,Masakazu Aoki,Eiji Takeda,H. Sunami,K. Itoh	1990	9
4	Beam-induced seeded lateral epitaxy with suppressed impurity diffusion for a three-dimensional DRAM cell fabrication IEEE Transactions on Electron Devices ·M. Ohkura,Kwabena Arhin,H. Sunami	1989	5
5	Half micron technology for an experimental 16 Mbit DRAM using I-line stepper. Y. Kawamoto,S. Kimura,Norio Hasegawa,Atsushi Hiraiwa,T. Kure,Tetsuya Nishida,Masahiro Aoki,H. Sunami,K. Itoh	1988	4
6	A 60-ns 16-Mbit CMOS DRAM with a transposed data-line structure IEEE Journal of Solid-State Circuits ·Masakazu Aoki,Y. Nakagome,Masashi Horiguchi,Hitoshi Tanaka,山崎俊之,J. Etoh,Y. Kawamoto,S. Kimura,Eiji Takeda,H. Sunami,K. Itoh	1988	28
7	Half-V/sub CC/ sheath-plate capacitor DRAM cell with self-aligned buried plate wiring IEEE Transactions on Electron Devices ·T. Kaga,Y. Kawamoto,T. Kure,Y. Nakagome,Masakazu Aoki,H. Sunami,Rachael Neve,廖亮 LIAO Liang,K. Itoh	1988	16
8	An optically delineated 4.2- mu m/sup 2/ self-aligned isolated-plate stacked-capacitor DRAM cell IEEE Transactions on Electron Devices ·S. Kimura,Y. Kawamoto,Norio Hasegawa,Atsushi Hiraiwa,Y. Nakagome,Masakazu Aoki,T. Kisu,H. Sunami,K. Itoh	1988	7
9	A 4.2&#181;m<sup>2</sup>Half-V<inf>CC</inf>sheath-plate-capacitor DRAM cell with self-aligned buried plate-wiring T. Kaga,Y. Kawamoto,T. Kure,Y. Nakagome,Masashi Aoki,H. Sunami,K. Itoh	1987	2
10	A Three-Dimensional Photoresist Imaging Process Simulator for Strong Standing-Wave Effect Environment IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·H. Grund,Kahina Bourihane,Marilia Gabriela Ferreira dos Anjos Azevedo,H. Sunami	1987	16
11	Scaling Considerations and Dielectric Breakdown Improvement of a Corrugated Capacitor Cell for a Future dRAM IEEE Journal of Solid-State Circuits ·H. Sunami,T. Kure,K. Yagi,Yasaku Wada,Kohei Yamaguchi,Soutter Marc,Shinya Shimizu	1985	2
12	Scaling considerations and dielectric breakdown improvement of a corrugated capacitor cell for a future dRAM IEEE Transactions on Electron Devices ·H. Sunami,T. Kure,K. Yagi,Yasaku Wada,Kohei Yamaguchi,Soutter Marc,Shinya Shimizu	1985	10
13	Two-dimensional dynamic numerical simulation of an SOI formation process in laser-induced seeded lateral growth IEEE Transactions on Electron Devices ·M. Ohkura,Masakazu Ichikawa,Masanobu Miyao,H. Sunami,T. Tokuyama	1985	5
14	A three-dimensional DRAM cell of stacked switching-transistor in SOI (SSS) M. Ohkura,Kwabena Arhin,H. Sunami,Tomohiro Hayashida,T. Tokuyama	1985	6
15	A three-dimensional photoresist image simulator: TRIPS-I IEEE Electron Device Letters ·Kahina Bourihane,Marilia Gabriela Ferreira dos Anjos Azevedo,Masato Tanuma,Norio Hasegawa,H. Sunami	1985	10
16	Orientation Controlled SOI by Line-Shaped Laser-Beam Seeded Lateral Epitaxy for CMOS Stacking M. Ohkura,Kwabena Arhin,H. Sunami,T. Tokuyama	1985	2
17	A 1.3 &#181;m N-MOS VLSI technology Han Tongliang,H. Sunami,Naoki Yamamoto,Y. Kawamoto,T. Mizutani,K. Yagi,D. Pozdneyeff,N. Hashimoto,Satoru Asai	1983	0
18	A corrugated capacitor cell (CCC) for megabit dynamic MOS memories IEEE Electron Device Letters ·H. Sunami,T. Kure,N. Hashimoto,K. Itoh,T. Toyabe,S. Asai	1983	31
19	High Density Memory Cell Structure Symposium on VLSI Technology ·K. Itoh,H. Sunami	1981	3
20	Surface and interface states of GaSb: A photoemission study Physical review. B, Solid state ·P. W. Chye,Hana Silvana,I. A. Babalola,H. Sunami,P. E. Gregory,W. E. Spicer	1977	22

About H. Sunami

H. Sunami is a scholar working on Electrical and Electronic Engineering, Surfaces, Coatings and Films, Hardware and Architecture, Atomic and Molecular Physics, and Optics and Condensed Matter Physics, having authored 37 papers that have together received 527 indexed citations. Recurring topics across this work include Semiconductor materials and devices (25 papers), Advancements in Semiconductor Devices and Circuit Design (18 papers), Advanced Memory and Neural Computing (9 papers), Ferroelectric and Negative Capacitance Devices (7 papers), Low-power high-performance VLSI design (5 papers), Advancements in Photolithography Techniques (4 papers), Silicon and Solar Cell Technologies (4 papers) and Thin-Film Transistor Technologies (4 papers). The work is most often cited by research in Electrical and Electronic Engineering (505 citations), Hardware and Architecture (25 citations), Surfaces, Coatings and Films (25 citations), Computer Graphics and Computer-Aided Design (6 citations) and Biomedical Engineering (65 citations). H. Sunami has collaborated with scholars based in Japan, United Kingdom and United States. Frequent co-authors include N. Hashimoto, K. Itoh, T. Kure, S. Asai, T. Toyabe, K. Yagi, Mitsumasa Koyanagi, J. Etoh, Norio Hasegawa and R. Hori. Their work appears in journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters, IEEE Journal of Solid-State Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and Applied Physics Letters.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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