Chi-Feng Wu

828 total citations
31 papers, 658 citations indexed

About

Chi-Feng Wu is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Control and Systems Engineering. According to data from OpenAlex, Chi-Feng Wu has authored 31 papers receiving a total of 658 indexed citations (citations by other indexed papers that have themselves been cited), including 26 papers in Electrical and Electronic Engineering, 25 papers in Hardware and Architecture and 4 papers in Control and Systems Engineering. Recurrent topics in Chi-Feng Wu's work include VLSI and Analog Circuit Testing (24 papers), Integrated Circuits and Semiconductor Failure Analysis (20 papers) and Radiation Effects in Electronics (9 papers). Chi-Feng Wu is often cited by papers focused on VLSI and Analog Circuit Testing (24 papers), Integrated Circuits and Semiconductor Failure Analysis (20 papers) and Radiation Effects in Electronics (9 papers). Chi-Feng Wu collaborates with scholars based in Taiwan and United States. Chi-Feng Wu's co-authors include Cheng‐Wen Wu, Chih-Tsun Huang, Jin-Fu Li, Jing-Reng Huang, Tsin‐Yuan Chang, Kuo-Liang Cheng, Chua‐Chin Wang, Kevin Kuan‐Shun Chiu, Jen-Chieh Yeh and Yung-Fa Chou and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, Electronics Letters and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

Chi-Feng Wu

31 papers receiving 617 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Chi-Feng Wu Taiwan	12	572	541	135	63	34	31	658
R. Rajsuman United States	12	513 0.9×	513 0.9×	80 0.6×	78 1.2×	22 0.6×	47	624
Benoit Nadeau-Dostie United States	14	633 1.1×	621 1.1×	38 0.3×	86 1.4×	13 0.4×	36	678
Kuo-Liang Cheng Taiwan	11	339 0.6×	337 0.6×	67 0.5×	57 0.9×	6 0.2×	23	388
Yung-Fa Chou Taiwan	14	602 1.1×	290 0.5×	83 0.6×	23 0.4×	76 2.2×	63	641
Jeff Rearick United States	12	594 1.0×	609 1.1×	27 0.2×	95 1.5×	12 0.4×	38	638
Kaviraj Chopra United States	17	851 1.5×	556 1.0×	59 0.4×	16 0.3×	64 1.9×	31	899
H. Guzmán-Miranda Spain	12	439 0.8×	295 0.5×	62 0.5×	40 0.6×	7 0.2×	50	472
Mirko Loghi Italy	14	223 0.4×	289 0.5×	246 1.8×	20 0.3×	42 1.2×	42	515
D. Josephson United States	9	444 0.8×	406 0.8×	45 0.3×	19 0.3×	23 0.7×	11	484
Paul Rosinger United Kingdom	17	643 1.1×	606 1.1×	157 1.2×	61 1.0×	9 0.3×	30	714

Countries citing papers authored by Chi-Feng Wu

Since Specialization

Citations

This map shows the geographic impact of Chi-Feng Wu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Chi-Feng Wu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Chi-Feng Wu more than expected).

Fields of papers citing papers by Chi-Feng Wu

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Chi-Feng Wu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Chi-Feng Wu. The network helps show where Chi-Feng Wu may publish in the future.

Co-authorship network of co-authors of Chi-Feng Wu

This figure shows the co-authorship network connecting the top 25 collaborators of Chi-Feng Wu. A scholar is included among the top collaborators of Chi-Feng Wu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Chi-Feng Wu. Chi-Feng Wu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Liu, Wei-Chang, et al.. (2015). Gb/s prototyping of 60GHz indoor wireless SC/OFDM transmitter and receiver on FPGA demo system. 6. 204–205. 2 indexed citations

Wu, Chi-Feng, et al.. (2014). Mask-cost-aware ECO routing. Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014. 1–4. 1 indexed citations

Wu, Chi-Feng, et al.. (2014). Apply high-level synthesis design and verification methodology on floating-point unit implementation. 1–4. 1 indexed citations

Chen, Ying-Yen, et al.. (2011). Monitoring gate and interconnect delay variations by using ring oscillators. 1–4. 1 indexed citations

Wu, Chi-Feng, et al.. (2008). On-chip interconnection design and SoC integration with OCP. 25–28. 8 indexed citations

Wu, Chi-Feng, et al.. (2007). Microprocessor Modeling and Simulation with SystemC. 1–4. 5 indexed citations

Huang, Chih-Tsun, Chi-Feng Wu, Jin-Fu Li, & Cheng‐Wen Wu. (2003). Built-in redundancy analysis for memory yield improvement. IEEE Transactions on Reliability. 52(4). 386–399. 163 indexed citations

Wang, Chua‐Chin, et al.. (2003). High fan-in dynamic cmos comparators with low transistor count. IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications. 50(9). 1216–1220. 27 indexed citations

Wu, Chi-Feng, Chih-Tsun Huang, & Cheng‐Wen Wu. (2003). RAMSES: a fast memory fault simulator. 165–173. 61 indexed citations

10.

Wu, Chi-Feng, et al.. (2002). A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters. 103–108. 18 indexed citations

11.

Wu, Chi-Feng, et al.. (2002). Error catch and analysis for semiconductor memories using March tests. 468–471. 6 indexed citations

12.

Wu, Chi-Feng, et al.. (2002). Fault simulation and test algorithm generation for random access memories. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21(4). 480–490. 34 indexed citations

13.

Wu, Chi-Feng, et al.. (2002). Simulation-based test algorithm generation and port scheduling for multi-port memories. 301–306. 1 indexed citations

14.

Wu, Chi-Feng, et al.. (2001). Simulation-based test algorithm generation and port scheduling for multi-port memories. 301–306. 9 indexed citations

15.

Wang, Chua‐Chin, et al.. (2000). A low-cost quadrature decoder/counter interface integrated circuit for AC induction motor server control. International Journal of Electronics. 87(9). 1053–1063. 3 indexed citations

16.

Wu, Chi-Feng, et al.. (1999). Testing and Diagnosing Dynamic Reconfigurable FPGA. VLSI design. 10(3). 321–333. 2 indexed citations

17.

Wu, Chi-Feng & Cheng‐Wen Wu. (1999). Testing interconnects of dynamic reconfigurable FPGAs. 279–282 vol.1. 4 indexed citations

18.

Wu, Chi-Feng, et al.. (1999). Dynamic NOR-NOR PLA design with IDDQ testability. International Journal of Electronics. 86(1). 79–85. 2 indexed citations

19.

Huang, Chih-Tsun, Jing-Reng Huang, Chi-Feng Wu, Cheng‐Wen Wu, & Tsin‐Yuan Chang. (1999). A programmable BIST core for embedded DRAM. IEEE Design & Test of Computers. 16(1). 59–70. 106 indexed citations

20.

Wang, Chua‐Chin, et al.. (1999). In-sawing-lane multi-level BIST for known gooddies of LCD drivers. Electronics Letters. 35(18). 1543–1544. 2 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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