Chua‐Chin Wang

2.9k total citations
318 papers, 2.1k citations indexed

About

Chua‐Chin Wang is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, Chua‐Chin Wang has authored 318 papers receiving a total of 2.1k indexed citations (citations by other indexed papers that have themselves been cited), including 277 papers in Electrical and Electronic Engineering, 125 papers in Biomedical Engineering and 35 papers in Hardware and Architecture. Recurrent topics in Chua‐Chin Wang's work include Analog and Mixed-Signal Circuit Design (108 papers), Low-power high-performance VLSI design (95 papers) and Advancements in Semiconductor Devices and Circuit Design (84 papers). Chua‐Chin Wang is often cited by papers focused on Analog and Mixed-Signal Circuit Design (108 papers), Low-power high-performance VLSI design (95 papers) and Advancements in Semiconductor Devices and Circuit Design (84 papers). Chua‐Chin Wang collaborates with scholars based in Taiwan, Philippines and India. Chua‐Chin Wang's co-authors include Doron Shmilovitz, Ching‐Li Lee, Chenn‐Jung Huang, Jianming Huang, Chia-Hung Yeh, Shaul Ozeri, Chih-Hsiang Huang, Li-Wei Kang, Chia‐Chen Lin and Chuan‐Yu Chang and has published in prestigious journals such as IEEE Transactions on Biomedical Engineering, Sensors and IEEE Journal of Solid-State Circuits.

In The Last Decade

Chua‐Chin Wang

282 papers receiving 2.0k citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Chua‐Chin Wang Taiwan 22 1.6k 690 234 214 171 318 2.1k
Hani Saleh United Arab Emirates 23 1.0k 0.6× 584 0.8× 267 1.1× 147 0.7× 139 0.8× 155 1.8k
Wang Ling Goh Singapore 23 1.8k 1.1× 924 1.3× 255 1.1× 285 1.3× 126 0.7× 183 2.4k
Hassan Mostafa Egypt 20 1.3k 0.8× 463 0.7× 268 1.1× 181 0.8× 301 1.8× 271 1.9k
Xuecheng Zou China 19 1.1k 0.7× 263 0.4× 268 1.1× 221 1.0× 175 1.0× 254 1.9k
Yejoong Kim United States 27 1.7k 1.1× 813 1.2× 253 1.1× 116 0.5× 262 1.5× 75 2.2k
Mingoo Seok United States 34 3.7k 2.3× 1.3k 1.9× 716 3.1× 218 1.0× 335 2.0× 186 4.2k
Masahiko Yoshimoto Japan 20 1.2k 0.8× 429 0.6× 389 1.7× 499 2.3× 253 1.5× 240 2.1k
Fei Qiao China 22 1.0k 0.7× 429 0.6× 135 0.6× 955 4.5× 90 0.5× 134 2.4k
Alicia Klinefelter United States 12 760 0.5× 241 0.3× 228 1.0× 220 1.0× 147 0.9× 19 1.0k
Shreyas Sen United States 29 1.6k 1.0× 1.1k 1.5× 695 3.0× 360 1.7× 487 2.8× 210 2.9k

Countries citing papers authored by Chua‐Chin Wang

Since Specialization
Citations

This map shows the geographic impact of Chua‐Chin Wang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Chua‐Chin Wang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Chua‐Chin Wang more than expected).

Fields of papers citing papers by Chua‐Chin Wang

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Chua‐Chin Wang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Chua‐Chin Wang. The network helps show where Chua‐Chin Wang may publish in the future.

Co-authorship network of co-authors of Chua‐Chin Wang

This figure shows the co-authorship network connecting the top 25 collaborators of Chua‐Chin Wang. A scholar is included among the top collaborators of Chua‐Chin Wang based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Chua‐Chin Wang. Chua‐Chin Wang is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
2.
Wang, Chua‐Chin, et al.. (2025). A 49.23% Power Reduction Active Gate Driver with Digital Multi-level Power Gating Control. Journal of Circuits Systems and Computers. 35(4).
3.
Wang, Chua‐Chin, et al.. (2025). A 4.447 mW at 100 MHz and 49.62% Uniqueness XNOR–XOR RO PUF ASIC Using 180-nm CMOS Process for IoT Security Applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 33(10). 2620–2629. 1 indexed citations
4.
Wang, Chua‐Chin, et al.. (2025). A 24.9% Power Reduction Active Gate Driver With Power Gating and Current Modulation for Power MOSFETs. IEEE Transactions on Circuits & Systems II Express Briefs. 72(11). 1640–1644.
5.
Chen, Jianjie, et al.. (2024). A Highly Reliable XNOR-XOR-RO PUF Design for IoT Security Applications. 143–147. 2 indexed citations
6.
Wang, Chua‐Chin, et al.. (2024). A single-chip PFM-controlled LED driver with 0.5% illuminance variation. Microelectronics Journal. 147. 106167–106167. 1 indexed citations
7.
Wang, Chua‐Chin, et al.. (2024). A 6-Gbps 16-nm FinFET CMOS I/O Buffer With Variation Insensitivity Ensured by Genetic Algorithm. IEEE Transactions on Circuits and Systems I Regular Papers. 71(11). 4961–4972.
8.
Tolentino, Lean Karlo S., et al.. (2024). A 6.25-MHz 3.4-mW Single Clock DPWM Technique Using Matrix Shift Array. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 32(5). 972–976. 1 indexed citations
9.
Wang, Chua‐Chin, et al.. (2024). A Wide Range 2-to-2048 Division Ratio Frequency Divider Using 40-nm CMOS Process. 1–4. 1 indexed citations
10.
11.
Chen, Weizhen, et al.. (2023). A 1-kb Sub-1 fJ/b Per Access CAM Design Using 40-nm CMOS Process. 50–54. 2 indexed citations
12.
Chou, Mitch M. C., et al.. (2023). 2-Level Miller Detection-Based High Side Gate Driver Design for Power MOSFETs. 266–270. 2 indexed citations
13.
Wang, Chua‐Chin, et al.. (2023). A 1.0 fJ energy/bit single‐ended 1 kb 6T SRAM implemented using 40 nm CMOS process. IET Circuits Devices & Systems. 17(2). 75–87. 4 indexed citations
14.
Tolentino, Lean Karlo S., et al.. (2023). A 210-MHz 4.23 fJ Energy/Bit 1-kb Asymmetrical Schmitt-Trigger-Based SRAM Using 40-nm CMOS Process. IEEE Transactions on Circuits & Systems II Express Briefs. 70(10). 3862–3866. 3 indexed citations
15.
Wang, Chua‐Chin, et al.. (2022). A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder. Circuits Systems and Signal Processing. 42(4). 2283–2304. 2 indexed citations
16.
Wang, Chua‐Chin, et al.. (2022). Single-chip DC–DC buck converter design based on PWM with high-efficiency in light load. International Journal of Electronics Letters. 11(3). 255–266. 2 indexed citations
17.
Wang, Chua‐Chin, et al.. (2022). A 40.96-GOPS 196.8-mW Digital Logic Accelerator Used in DNN for Underwater Object Recognition. IEEE Transactions on Circuits and Systems I Regular Papers. 69(12). 4860–4871. 2 indexed citations
18.
Wang, Chua‐Chin, et al.. (2021). An adaptive constant current and voltage mode P&O-based Maximum Power Point Tracking controller IC using 0.5-μmHV CMOS. Microelectronics Journal. 118. 105295–105295. 11 indexed citations
19.
Wang, Chua‐Chin, et al.. (2021). A Single-Ended Low Power 16-nm FinFET 6T SRAM Design With PDP Reduction Circuit. IEEE Transactions on Circuits & Systems II Express Briefs. 68(12). 3478–3482. 9 indexed citations
20.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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