R. Rajsuman

950 total citations
47 papers, 624 citations indexed

About

R. Rajsuman is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Control and Systems Engineering. According to data from OpenAlex, R. Rajsuman has authored 47 papers receiving a total of 624 indexed citations (citations by other indexed papers that have themselves been cited), including 44 papers in Hardware and Architecture, 34 papers in Electrical and Electronic Engineering and 12 papers in Control and Systems Engineering. Recurrent topics in R. Rajsuman's work include VLSI and Analog Circuit Testing (43 papers), Integrated Circuits and Semiconductor Failure Analysis (25 papers) and Engineering and Test Systems (10 papers). R. Rajsuman is often cited by papers focused on VLSI and Analog Circuit Testing (43 papers), Integrated Circuits and Semiconductor Failure Analysis (25 papers) and Engineering and Test Systems (10 papers). R. Rajsuman collaborates with scholars based in United States, Japan and Belgium. R. Rajsuman's co-authors include Yashwant K. Malaiya, Anura P. Jayasumana, Francky Catthoor, Jonathan L. Katz, Koichi Yamashita, Jaebum Park, Scott Davidson, Erik Jan Marinissen, Y. Zorian and Michelle Collins and has published in prestigious journals such as Proceedings of the IEEE, IEEE Journal of Solid-State Circuits and Electronics Letters.

In The Last Decade

R. Rajsuman

41 papers receiving 555 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
R. Rajsuman United States 12 513 513 80 78 22 47 624
Chi-Feng Wu Taiwan 12 541 1.1× 572 1.1× 135 1.7× 63 0.8× 34 1.5× 31 658
Alain Vachoux Switzerland 9 210 0.4× 200 0.4× 56 0.7× 76 1.0× 46 2.1× 34 349
K. Baker Netherlands 11 311 0.6× 321 0.6× 32 0.4× 27 0.3× 16 0.7× 30 371
Kaviraj Chopra United States 17 556 1.1× 851 1.7× 59 0.7× 16 0.2× 64 2.9× 31 899
Mango C.-T. Chao Taiwan 14 335 0.7× 454 0.9× 38 0.5× 26 0.3× 20 0.9× 78 515
Artur Jutman Estonia 12 401 0.8× 372 0.7× 49 0.6× 77 1.0× 11 0.5× 81 462
S. Cherubal United States 13 540 1.1× 598 1.2× 23 0.3× 71 0.9× 79 3.6× 22 651
E. Malavasi United States 13 509 1.0× 694 1.4× 54 0.7× 19 0.2× 80 3.6× 41 753
Yuejian Wu Canada 10 263 0.5× 289 0.6× 23 0.3× 25 0.3× 12 0.5× 28 318
A. Krstić United States 19 869 1.7× 877 1.7× 31 0.4× 58 0.7× 19 0.9× 32 945

Countries citing papers authored by R. Rajsuman

Since Specialization
Citations

This map shows the geographic impact of R. Rajsuman's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by R. Rajsuman with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites R. Rajsuman more than expected).

Fields of papers citing papers by R. Rajsuman

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by R. Rajsuman. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by R. Rajsuman. The network helps show where R. Rajsuman may publish in the future.

Co-authorship network of co-authors of R. Rajsuman

This figure shows the co-authorship network connecting the top 25 collaborators of R. Rajsuman. A scholar is included among the top collaborators of R. Rajsuman based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with R. Rajsuman. R. Rajsuman is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
2.
Adham, Saman, Michelle Collins, Erik Jan Marinissen, et al.. (2005). Preliminary Outline of the IEEE PI 500 Scalable Architecture for Testing Embedded Cores. 483–488.
3.
Rajsuman, R., et al.. (2005). Open architecture test system: system architecture and design. 403–412. 6 indexed citations
4.
Rajsuman, R.. (2005). An Architecture To Test Random Access Memories. 144–147.
5.
Rajsuman, R.. (2003). Extending EDA environment from design to test. 386–391. 2 indexed citations
6.
Rajsuman, R.. (2003). An algorithm and design to test random access memories. 1. 439–442. 4 indexed citations
7.
Rajsuman, R.. (2003). Architecture, design, and application of an event-based test system. IEEE Transactions on Instrumentation and Measurement. 52(5). 1408–1427. 2 indexed citations
8.
Rajsuman, R.. (2002). Algorithms to test PSF and coupling faults in random access memories. 135. 49–54. 1 indexed citations
9.
Katz, Jonathan L. & R. Rajsuman. (2002). A new paradigm in test for the next millennium. 468–476. 11 indexed citations
10.
Rajsuman, R., Anura P. Jayasumana, Yashwant K. Malaiya, & Jaebum Park. (2002). An analysis and testing of operation induced faults in MOS VLSI. 137–142. 2 indexed citations
11.
Rajsuman, R., et al.. (2002). Test and repair of large embedded DRAMs. I. 163–172. 15 indexed citations
12.
Rajsuman, R.. (2002). Testing The Tester. 27. 2 indexed citations
13.
Rajsuman, R.. (2001). Design and test of large embedded memories: An overview. IEEE Design & Test of Computers. 18(3). 16–27. 71 indexed citations
14.
Rajsuman, R.. (1992). Digital Hardware Testing: Transistor-Level Fault Modeling and Testing. 11 indexed citations
15.
Rajsuman, R.. (1991). New algorithm for testing random access memories. Electronics Letters. 27(7). 574–575. 2 indexed citations
16.
Jayasumana, Anura P., Yashwant K. Malaiya, & R. Rajsuman. (1991). Design of CMOS circuits for stuck-open fault testability. IEEE Journal of Solid-State Circuits. 26(1). 58–61. 23 indexed citations
17.
Rajsuman, R., et al.. (1990). On the testing of microprogrammed processor. International Symposium on Microarchitecture. 260–266.
18.
Rajsuman, R., Yashwant K. Malaiya, & Anura P. Jayasumana. (1990). Reprogrammable FPLA with universal test set. IEE Proceedings E Computers and Digital Techniques. 137(6). 437–437. 2 indexed citations
19.
Rajsuman, R., Anura P. Jayasumana, & Yashwant K. Malaiya. (1989). CMOS open-fault detection in the presence of glitches and timing skews. IEEE Journal of Solid-State Circuits. 24(4). 1055–1061. 8 indexed citations
20.
Rajsuman, R.. (1989). Design of reprogrammable FPLA. Electronics Letters. 25(11). 715–716. 5 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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