C. Hora

650 total citations
27 papers, 507 citations indexed

About

C. Hora is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Industrial and Manufacturing Engineering. According to data from OpenAlex, C. Hora has authored 27 papers receiving a total of 507 indexed citations (citations by other indexed papers that have themselves been cited), including 27 papers in Electrical and Electronic Engineering, 22 papers in Hardware and Architecture and 2 papers in Industrial and Manufacturing Engineering. Recurrent topics in C. Hora's work include Integrated Circuits and Semiconductor Failure Analysis (27 papers), VLSI and Analog Circuit Testing (22 papers) and Semiconductor materials and devices (10 papers). C. Hora is often cited by papers focused on Integrated Circuits and Semiconductor Failure Analysis (27 papers), VLSI and Analog Circuit Testing (22 papers) and Semiconductor materials and devices (10 papers). C. Hora collaborates with scholars based in Netherlands, Spain and Finland. C. Hora's co-authors include S. Eichenberger, B. Kruseman, A.K. Majhi, M. Lousberg, G. Gronthoud, H. Hashempour, W. G. MOORE, R. Rodríguez‐Montañés, Joan Figueras and Daniel Arumí and has published in prestigious journals such as Electronics Letters, IEEE Transactions on Instrumentation and Measurement and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

C. Hora

27 papers receiving 476 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
C. Hora Netherlands	13	482	447	36	29	11	27	507
B. Kruseman Netherlands	14	576 1.2×	516 1.2×	31 0.9×	14 0.5×	12 1.1×	35	600
S. Eichenberger Netherlands	12	543 1.1×	509 1.1×	22 0.6×	19 0.7×	9 0.8×	25	567
Sreejit Chakravarty United States	13	507 1.1×	485 1.1×	55 1.5×	17 0.6×	27 2.5×	57	538
Huaxing Tang United States	13	497 1.0×	488 1.1×	52 1.4×	75 2.6×	17 1.5×	28	519
D.B.I. Feltham United States	9	317 0.7×	308 0.7×	30 0.8×	13 0.4×	17 1.5×	13	344
I. Hartanto United States	8	357 0.7×	373 0.8×	68 1.9×	12 0.4×	38 3.5×	15	386
Chris Schuermyer United States	11	407 0.8×	400 0.9×	39 1.1×	72 2.5×	24 2.2×	19	435
Srikanth Venkataraman United States	11	387 0.8×	395 0.9×	42 1.2×	23 0.8×	43 3.9×	33	408
Yuejian Wu Canada	10	289 0.6×	263 0.6×	25 0.7×	21 0.7×	6 0.5×	28	318
R. Raina United States	13	391 0.8×	389 0.9×	58 1.6×	14 0.5×	16 1.5×	29	445

Countries citing papers authored by C. Hora

Since Specialization

Citations

This map shows the geographic impact of C. Hora's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by C. Hora with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites C. Hora more than expected).

Fields of papers citing papers by C. Hora

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by C. Hora. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by C. Hora. The network helps show where C. Hora may publish in the future.

Co-authorship network of co-authors of C. Hora

This figure shows the co-authorship network connecting the top 25 collaborators of C. Hora. A scholar is included among the top collaborators of C. Hora based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with C. Hora. C. Hora is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Arumí, Daniel, R. Rodríguez‐Montañés, Joan Figueras, et al.. (2013). Diagnosis of Interconnect Full Open Defects in the Presence of Gate Leakage Currents. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32(2). 301–312. 1 indexed citations

Kruseman, B., et al.. (2012). Defect Oriented Testing for Analog/Mixed-Signal Designs. IEEE Design & Test of Computers. 29(5). 72–80. 13 indexed citations

Hashempour, H., et al.. (2011). Test time reduction in analogue/mixed-signal devices by defect oriented testing: An industrial example. 1–6. 20 indexed citations

Rodríguez‐Montañés, R., et al.. (2010). Diagnosis of full open defects in interconnect lines with fan-out. RECERCAT (Consorci de Serveis Universitaris de Catalunya). 233–238. 7 indexed citations

Arumí, Daniel, R. Rodríguez‐Montañés, Joan Figueras, et al.. (2010). Gate Leakage Impact on Full Open Defects in Interconnect Lines. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 19(12). 2209–2220. 5 indexed citations

Eichenberger, S., et al.. (2008). Towards a World Without Test Escapes: The Use of Volume Diagnosis to Improve Test Quality. 29 indexed citations

Arumí, Daniel, R. Rodríguez‐Montañés, Joan Figueras, et al.. (2008). Full Open Defects in Nanometric CMOS. 299. 119–124. 10 indexed citations

Rodríguez‐Montañés, R., Daniel Arumí, Joan Figueras, et al.. (2008). Time-dependent Behaviour of Full Open Defects in Interconnect Lines. 13. 1–10. 5 indexed citations

Rodríguez‐Montañés, R., Daniel Arumí, Joan Figueras, et al.. (2007). Impact of gate tunnelling leakage on CMOS circuits with full open defects. Electronics Letters. 43(21). 1140–1142. 11 indexed citations

10.

Arumí, Daniel, R. Rodríguez‐Montañés, Joan Figueras, et al.. (2007). Diagnosis of Bridging Defects Based on Current Signatures at Low Power Supply Voltages. 145–150. 7 indexed citations

11.

Rodríguez‐Montañés, R., Daniel Arumí, Joan Figueras, et al.. (2007). Diagnosis of Full Open Defects in Interconnecting Lines. 158–166. 20 indexed citations

12.

Moore, W. R., et al.. (2007). Extending gate-level diagnosis tools to CMOS intra-gate faults. IET Computers & Digital Techniques. 1(6). 685–693. 11 indexed citations

13.

Arumí, Daniel, R. Rodríguez‐Montañés, Joan Figueras, et al.. (2007). I _DDQ -based diagnosis at very low voltage (VLV) for bridging defects. Electronics Letters. 43(5). 273–274. 7 indexed citations

14.

MOORE, W. G., et al.. (2006). A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis. 266–271. 22 indexed citations

15.

MOORE, W. G., et al.. (2006). A novel stuck-at based method for transistor stuck-open fault diagnosis. 378–386. 28 indexed citations

16.

Vermeulen, Bart, et al.. (2005). Trends in testing integrated circuits. 688–697. 25 indexed citations

17.

Kruseman, B., et al.. (2005). Systematic defects in deep sub-micron technologies. 290–299. 58 indexed citations

18.

Hora, C. & S. Eichenberger. (2004). Towards High Accuracy Fault Diagnosis of Digital Circuits. Proceedings - International Symposium for Testing and Failure Analysis. 30873. 47–51. 3 indexed citations

19.

Hora, C., et al.. (2003). On a Statistical Fault Diagnosis Approach Enabling Fast Yield Ramp-Up. Journal of Electronic Testing. 19(4). 369–376. 10 indexed citations

20.

Majhi, A.K., et al.. (2003). Improving diagnostic resolution of delay faults using path delay fault model. 345–350. 6 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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