Greg Yeric

2.0k total citations · 1 hit paper
45 papers, 1.4k citations indexed

About

Greg Yeric is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Materials Chemistry. According to data from OpenAlex, Greg Yeric has authored 45 papers receiving a total of 1.4k indexed citations (citations by other indexed papers that have themselves been cited), including 43 papers in Electrical and Electronic Engineering, 11 papers in Hardware and Architecture and 5 papers in Materials Chemistry. Recurrent topics in Greg Yeric's work include Semiconductor materials and devices (25 papers), Advancements in Photolithography Techniques (16 papers) and Advancements in Semiconductor Devices and Circuit Design (16 papers). Greg Yeric is often cited by papers focused on Semiconductor materials and devices (25 papers), Advancements in Photolithography Techniques (16 papers) and Advancements in Semiconductor Devices and Circuit Design (16 papers). Greg Yeric collaborates with scholars based in United States, United Kingdom and Switzerland. Greg Yeric's co-authors include Brian Cline, Saurabh Sinha, L. Shifren, Vikas Chandra, Lawrence T. Clark, Vinay Vashishtha, Chandarasekaran Ramamurthy, Yu Cao, A.F. Tasch and Sung Kyu Lim and has published in prestigious journals such as IEEE Transactions on Electron Devices, IEEE Electron Device Letters and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

Greg Yeric

43 papers receiving 1.4k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

ASAP7: A 7-nm finFET predictive process design kit

2016 459 citations Lawrence T. Clark, Vinay Vashishtha et al. Microelectronics Journal profile →

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Greg Yeric United States	18	1.3k	338	137	116	99	45	1.4k
Brian Cline United States	20	1.5k 1.2×	429 1.3×	153 1.1×	169 1.5×	90 0.9×	60	1.6k
Lawrence T. Clark United States	22	2.0k 1.6×	899 2.7×	233 1.7×	187 1.6×	103 1.0×	152	2.3k
Mottaqiallah Taouil Netherlands	21	1.4k 1.1×	376 1.1×	120 0.9×	55 0.5×	25 0.3×	157	1.6k
Payman Zarkesh-Ha United States	18	884 0.7×	244 0.7×	184 1.3×	75 0.6×	56 0.6×	114	1.0k
Peter Debacker Belgium	19	817 0.6×	152 0.4×	147 1.1×	91 0.8×	63 0.6×	73	924
Andrea Calimera Italy	18	762 0.6×	224 0.7×	88 0.6×	64 0.6×	57 0.6×	116	957
Pieter Weckx Belgium	22	1.8k 1.4×	184 0.5×	75 0.5×	128 1.1×	130 1.3×	140	1.9k
Daeyeon Kim United States	16	905 0.7×	156 0.5×	112 0.8×	221 1.9×	42 0.4×	54	1.1k
Praveen Raghavan Belgium	19	1.5k 1.1×	275 0.8×	285 2.1×	230 2.0×	199 2.0×	142	1.7k
Kerry Bernstein United States	9	867 0.7×	267 0.8×	209 1.5×	97 0.8×	81 0.8×	11	969

Countries citing papers authored by Greg Yeric

Since Specialization

Citations

This map shows the geographic impact of Greg Yeric's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Greg Yeric with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Greg Yeric more than expected).

Fields of papers citing papers by Greg Yeric

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Greg Yeric. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Greg Yeric. The network helps show where Greg Yeric may publish in the future.

Co-authorship network of co-authors of Greg Yeric

This figure shows the co-authorship network connecting the top 25 collaborators of Greg Yeric. A scholar is included among the top collaborators of Greg Yeric based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Greg Yeric. Greg Yeric is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Chang, Kyungwook, Saurabh Sinha, Brian Cline, Greg Yeric, & Sung Kyu Lim. (2021). Design-Aware Partitioning-Based 3-D IC Design Flow With 2-D Commercial Tools. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 41(3). 410–423. 3 indexed citations

Sinha, Saurabh, et al.. (2017). Replacing copper interconnects with graphene at a 7-nm node. 1–3. 28 indexed citations

Xu, Xiaoqing, et al.. (2017). Standard cell library design and optimization methodology for ASAP7 PDK: (Invited paper). 999–1004. 29 indexed citations

Chang, Kyungwook, Shidhartha Das, Saurabh Sinha, et al.. (2017). Frequency and time domain analysis of power delivery network for monolithic 3D ICs. 14 indexed citations

Aitken, Robert, Vikas Chandra, Brian Cline, et al.. (2016). Predicting future complementary metal–oxide–semiconductor technology – challenges and approaches. IET Computers & Digital Techniques. 10(6). 315–322.

Sinha, Saurabh, et al.. (2016). Four-tier Monolithic 3D ICs. 70–75. 7 indexed citations

Clark, Lawrence T., Vinay Vashishtha, L. Shifren, et al.. (2016). ASAP7: A 7-nm finFET predictive process design kit. Microelectronics Journal. 53. 105–115. 459 indexed citations breakdown →

Lee, Chi-Shuen, Brian Cline, Saurabh Sinha, Greg Yeric, & H.‐S. Philip Wong. (2016). 32-bit Processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance. 28.3.1–28.3.4. 36 indexed citations

Wang, Xingsheng, Vihar Georgiev, Salvatore Amoroso, et al.. (2015). Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors. IEEE Transactions on Electron Devices. 62(10). 3229–3236. 20 indexed citations

10.

Yeric, Greg. (2015). Moore's law at 50: Are we planning for retirement?. 1.1.1–1.1.8. 51 indexed citations

11.

Xu, Xiaoqing, Brian Cline, Greg Yeric, Bei Yu, & David Z. Pan. (2015). A systematic framework for evaluating standard cell middle-of-line (MOL) robustness for multiple patterning. Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE. 9427. 942707–942707. 4 indexed citations

12.

Yeric, Greg. (2014). Processor yield at 14nm and beyond. 98. 111–116. 1 indexed citations

13.

Xu, Xiaoqing, Brian Cline, Greg Yeric, Bei Yu, & David Z. Pan. (2014). Self-aligned double patterning aware pin access and standard cell layout co-optimization. 101–108. 25 indexed citations

14.

Aitken, Robert, Greg Yeric, Brian Cline, et al.. (2014). Physical design and FinFETs. 65–68. 19 indexed citations

15.

Adamu-Lema, Fikru, Salvatore Amoroso, Xingsheng Wang, et al.. (2014). The discrepancy between the uniform and variability aware atomistic TCAD simulations of decananometer bulk MOSFETs and FinFETs. ENLIGHTEN (Jurnal Bimbingan dan Konseling Islam). 285–288.

16.

Yeric, Greg, et al.. (2013). The past present and future of design-technology co-optimization. 1–8. 23 indexed citations

17.

Sinha, Saurabh, Greg Yeric, Vikas Chandra, Brian Cline, & Yu Cao. (2012). Exploring sub-20nm FinFET design with predictive technology models. 283–288. 246 indexed citations

18.

Fox, Stephen R., W. Cote, Greg Yeric, et al.. (2008). A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software. IEEE Transactions on Semiconductor Manufacturing. 21(2). 161–168. 7 indexed citations

19.

Fox, Stephen R., W. Cote, Greg Yeric, et al.. (2006). A 65nm random and systematic yield ramp infrastructure utilizing a specialized addressable array with integrated analysis software. 104–109. 14 indexed citations

20.

Yue, C. Patrick, et al.. (1993). Improved universal MOSFET electron mobility degradation models for circuit simulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 12(10). 1542–1546. 8 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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