Y. Hiruta

441 total citations
39 papers, 331 citations indexed

About

Y. Hiruta is a scholar working on Electrical and Electronic Engineering, Mechanical Engineering and Hardware and Architecture. According to data from OpenAlex, Y. Hiruta has authored 39 papers receiving a total of 331 indexed citations (citations by other indexed papers that have themselves been cited), including 37 papers in Electrical and Electronic Engineering, 6 papers in Mechanical Engineering and 4 papers in Hardware and Architecture. Recurrent topics in Y. Hiruta's work include Electronic Packaging and Soldering Technologies (24 papers), 3D IC and TSV technologies (17 papers) and Electromagnetic Compatibility and Noise Suppression (6 papers). Y. Hiruta is often cited by papers focused on Electronic Packaging and Soldering Technologies (24 papers), 3D IC and TSV technologies (17 papers) and Electromagnetic Compatibility and Noise Suppression (6 papers). Y. Hiruta collaborates with scholars based in Japan, South Korea and United States. Y. Hiruta's co-authors include Michihiko Kitao, Shôji Yamada, K. Kanzaki, M. Miura, K. Maeguchi, Toshio Sudô, T. Sudô, T. Okada, Koji Matsumoto and F. Matsuoka and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, Applied Surface Science and IEEE Transactions on Electron Devices.

In The Last Decade

Y. Hiruta

36 papers receiving 302 citations

Peers

Countries citing papers authored by Y. Hiruta

Since Specialization

Citations

This map shows the geographic impact of Y. Hiruta's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Y. Hiruta with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Y. Hiruta more than expected).

Fields of papers citing papers by Y. Hiruta

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Y. Hiruta. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Y. Hiruta. The network helps show where Y. Hiruta may publish in the future.

Co-authorship network of co-authors of Y. Hiruta

This figure shows the co-authorship network connecting the top 25 collaborators of Y. Hiruta. A scholar is included among the top collaborators of Y. Hiruta based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Y. Hiruta. Y. Hiruta is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Reliability Improvement of Cu-Wire Bonded Lead Frame Package for Automotive Applications 2017 ·(unknown), Toru Takahashi, (unknown), (unknown), (unknown), (unknown), Y. Hiruta	6
2	A new embedded die package — WFOP™ 2014 ·Tomoko Takahashi, Hiroshi Inoue, (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), Akio Katsumata, Y. Hiruta	2
3	IMC study on Cu wirebond failures under high humidity conditions 2011 ·(unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), Akio Katsumata, Y. Hiruta	15
4	Design optimization of wiring substrate in a CMOS-based multichip module 2003 ·(unknown), (unknown), Kentaro Kato, Y. Hiruta, (unknown)	0
5	Electrical characterization of packaging environment using switching noise generating vehicle 2002 ·(unknown), M. Miura, (unknown), Y. Hiruta	9
6	A new bonding mechanism of 50 μm pitch TAB-ILB with 0.25 μm Sn plated Cu lead 2002 ·(unknown), (unknown), Hiroshi Tazawa, (unknown), Y. Hiruta, T. Sudô	0
7	Eutectic solder flip chip technology-bumping and assembly process development for CSP/BGA 2002 ·Hideo Aoki, (unknown), (unknown), (unknown), (unknown), Masahiro Miyata, (unknown), Y. Hiruta	7
8	A 300 MIPS, 300 MFLOPS four-issue CMOS superscalar microprocessor 2002 ·(unknown), S. Tanaka, K. Sawada, M. Nagamatsu, (unknown), T. Takayanagi, (unknown), (unknown), Koji Miyamoto, Y. Hiruta, Ping‐Yu Hsu, Paul Rodman, (unknown), (unknown), (unknown), (unknown), (unknown)	0
9	Plating Technologies for Electroplating Industries. Bump Process Technology for LSI Wafer. 1998 ·Journal of The Surface Finishing Society of Japan ·(unknown), (unknown), Y. Hiruta	2
10	Effectiveness of Thin‐film Barrier Metals for Eutectic Solder Bumps 1997 ·Microelectronics International ·(unknown), (unknown), Hiroshi Yamada, (unknown), (unknown), T. Okada, Hideo Aoki, Y. Hiruta, T. Sudô	9
11	Flip-Chip Bonding Process for CSTP Interconnected by Eutectic Solder Bumps, 1996 ·(unknown), (unknown), (unknown), Hiroshi Tazawa, (unknown), (unknown), T. Okada, Y. Hiruta, T. Sudô, Toshio Sudô	2
12	Simplified and practical estimation of package cracking during reflow soldering process 1994 ·(unknown), (unknown), (unknown), Koji Matsumoto, Y. Hiruta, T. Sudô	28
13	Minimization of Effective Inductance of Ground Plane and Experimental Simultaneous Switching Noise in a Multilayer VLSI Package 1992 ·Y. Hiruta, (unknown), (unknown), Toshio Sudô	3
14	Optimized Ground Pin Assignment in a Multi-layer Package to Minimize Simultaneous Switching Noise 1992 ·Y. Hiruta, (unknown), (unknown), Toshio Sudô	4
15	Interface state generation under long-term positive-bias temperature stress for a p/sup +/ poly gate MOS structure 1989 ·IEEE Transactions on Electron Devices ·Y. Hiruta, Hiroshi Iwai, F. Matsuoka, (unknown), K. Maeguchi, K. Kanzaki	20
16	+ BT Instability in P<sup>+</sup>poly gate MOS structure 1987 ·Y. Hiruta, F. Matsuoka, (unknown), (unknown), K. Maeguchi, K. Kanzaki	2
17	Impact of hot electron trapping on half micron PMOSFETs with p<sup>+</sup>poly Si gate 1986 ·Y. Hiruta, K. Maeguchi, K. Kanzaki	16
18	Warm Electron Coefficient ofn-InSb 1985 ·Journal of the Physical Society of Japan ·(unknown), Y. Hiruta, (unknown)	1
19	Relief of hot carrier constraint on submicron CMOS devices by use of a buried channel structure 1985 ·(unknown), Y. Hiruta, T. Noguchi, (unknown), K. Maeguchi, K. Kanzaki	8
20	Electrochromic Absorption Spectra of Mo_cW_1-cO₃ Films 1985 ·Japanese Journal of Applied Physics ·Shôji Yamada, Y. Hiruta, Norihiro Suzuki, Kazuo Urabe, Michihiko Kitao, K. Toyoda	7

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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