T. Takayanagi

402 total citations
19 papers, 266 citations indexed

About

T. Takayanagi is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, T. Takayanagi has authored 19 papers receiving a total of 266 indexed citations (citations by other indexed papers that have themselves been cited), including 14 papers in Electrical and Electronic Engineering, 8 papers in Hardware and Architecture and 6 papers in Computer Networks and Communications. Recurrent topics in T. Takayanagi's work include Low-power high-performance VLSI design (11 papers), Parallel Computing and Optimization Techniques (7 papers) and Interconnection Networks and Systems (6 papers). T. Takayanagi is often cited by papers focused on Low-power high-performance VLSI design (11 papers), Parallel Computing and Optimization Techniques (7 papers) and Interconnection Networks and Systems (6 papers). T. Takayanagi collaborates with scholars based in Japan, United States and South Korea. T. Takayanagi's co-authors include Tadahiro Kuroda, Hiroyuki Hara, Ana Sonia Leon, M. Hamada, Hideho Arakida, Hiroki Nakamura, T. Terazawa, Nobuya Machida, Jinuk Luke Shin and Masafumi Takahashi and has published in prestigious journals such as IEEE Journal of Solid-State Circuits.

In The Last Decade

T. Takayanagi

17 papers receiving 256 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
T. Takayanagi Japan 9 167 100 77 76 55 19 266
M. Hamada Japan 7 180 1.1× 90 0.9× 116 1.5× 94 1.2× 53 1.0× 9 282
T. Terazawa Japan 9 240 1.4× 136 1.4× 131 1.7× 104 1.4× 75 1.4× 11 363
José Luís Güntzel Brazil 9 166 1.0× 112 1.1× 126 1.6× 115 1.5× 18 0.3× 80 287
K. Furuta Japan 8 206 1.2× 94 0.9× 55 0.7× 43 0.6× 44 0.8× 16 280
N. Demassieux France 6 84 0.5× 61 0.6× 186 2.4× 164 2.2× 50 0.9× 28 285
Hideho Arakida Japan 11 263 1.6× 243 2.4× 147 1.9× 122 1.6× 172 3.1× 18 485
H.-J. Stolberg Germany 11 48 0.3× 136 1.4× 162 2.1× 134 1.8× 99 1.8× 23 289
F.W. Hoeksema Netherlands 8 121 0.7× 20 0.2× 131 1.7× 131 1.7× 134 2.4× 35 300
D. Liu Sweden 8 260 1.6× 142 1.4× 34 0.4× 18 0.2× 107 1.9× 27 362
Eddie Hung Canada 11 227 1.4× 258 2.6× 18 0.2× 37 0.5× 48 0.9× 28 311

Countries citing papers authored by T. Takayanagi

Since Specialization
Citations

This map shows the geographic impact of T. Takayanagi's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by T. Takayanagi with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites T. Takayanagi more than expected).

Fields of papers citing papers by T. Takayanagi

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by T. Takayanagi. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by T. Takayanagi. The network helps show where T. Takayanagi may publish in the future.

Co-authorship network of co-authors of T. Takayanagi

This figure shows the co-authorship network connecting the top 25 collaborators of T. Takayanagi. A scholar is included among the top collaborators of T. Takayanagi based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with T. Takayanagi. T. Takayanagi is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

19 of 19 papers shown
1.
2.
Takayanagi, T., Jinuk Luke Shin, Ha Pham, et al.. (2005). A dual-core 64-bit ultraSPARC microprocessor for dense server applications. IEEE Journal of Solid-State Circuits. 40(1). 7–18. 21 indexed citations
3.
Takayanagi, T., Jinuk Luke Shin, Ha Pham, et al.. (2004). A dual-core 64 b UltraSPARC microprocessor for dense server applications. 58–513. 2 indexed citations
4.
Takayanagi, T., et al.. (2004). Deep-submicron design challenges for a dual-core 64b UltraSPARC microprocessor implementation. 147–150. 3 indexed citations
5.
Takayanagi, T., et al.. (2004). A dual-core 64b ultraSPARC microprocessor for dense server applications. 673–677. 10 indexed citations
6.
Takayanagi, T., K. Sawada, Masaru Takahashi, et al.. (2002). 2.6 Gbyte/sec bandwidth cache/TLB macro for high-performance RISC processor. 10.2/1–10.2/4. 3 indexed citations
7.
Takayanagi, T., et al.. (2002). Throughput enhancement strategy of maskless electron beam direct writing for logic device. 833–836. 18 indexed citations
8.
Nishikawa, Takafumi, Masafumi Takahashi, M. Hamada, et al.. (2002). A 60 MHz 240 mW MPEG-4 video-phone LSI with 16 Mb embedded DRAM. 230–231,. 25 indexed citations
9.
Takayanagi, T., K. Sawada, T. Sakurai, et al.. (2002). Embedded memory design for a four issue superscaler RISC microprocessor. 585–590.
10.
Takayanagi, T., K. Nogami, F. Hatori, et al.. (2002). 350 MHz time-multiplexed 8-port SRAM and word size variable multiplier for multimedia DSP. 150–151,. 3 indexed citations
11.
Tanaka, S., K. Sawada, M. Nagamatsu, et al.. (2002). A 300 MIPS, 300 MFLOPS four-issue CMOS superscalar microprocessor. 204–205.
12.
Hara, Hiroyuki, et al.. (2002). A bit-line leakage compensation scheme for low-voltage SRAM's. 70–71. 14 indexed citations
13.
Hara, Hiroyuki, et al.. (2001). A bitline leakage compensation scheme for low-voltage SRAMs. IEEE Journal of Solid-State Circuits. 36(5). 726–734. 59 indexed citations
14.
Takahashi, Masafumi, M. Hamada, T. Takayanagi, et al.. (2000). A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM. IEEE Journal of Solid-State Circuits. 35(11). 1713–1721. 68 indexed citations
15.
Sawada, K., T. Takayanagi, K. Nogami, et al.. (1990). A 5 ns 369 kb port-configurable embedded SRAM with 0.5 mu m CMOS gate array. 226–227. 4 indexed citations
16.
Nogami, K., T. Sakurai, K. Sawada, et al.. (1990). A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC. IEEE Journal of Solid-State Circuits. 25(1). 100–108. 9 indexed citations
17.
Sawada, K., T. Sakurai, K. Nogami, et al.. (1989). A 32 kbyte integrated cache memory. IEEE Journal of Solid-State Circuits. 24(4). 881–888. 7 indexed citations
18.
Nogami, K., K. Maeguchi, Kiyoshi Kobayashi, et al.. (1988). Architecture and Design Methodology of 32KByte Integrated Cache Memory. 98–101. 1 indexed citations
19.
Sakurai, Takayasu, K. Nogami, K. Sawada, et al.. (1987). A Circuit Design of 32KByte Integrated Cache Memory. 1 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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