T. Takayanagi
- Electrical and Electronic Engineering
- Hardware and Architecture top 5%
- Signal Processing top 10%
- Computer Vision and Pattern Recognition top 10%
- Computer Networks and Communications
- Co-authors
- Tadahiro KurodaHiroyuki HaraJinuk Luke ShinM. HamadaKenji OhmoriT. FuruyamaNobuya MachidaT. Terazawa
- Topics
- Low-power high-performance VLSI design (11 papers)Parallel Computing and Optimization Techniques (7 papers)Interconnection Networks and Systems (6 papers)
- Journals
- IEEE Journal of Solid-State Circuits
- Partner nations
- JapanUnited StatesSouth Korea
In The Last Decade
T. Takayanagi
17 papers receiving 256 citations
Peers
Comparison fields: 5 of 26
- Electrical and Electronic Engineering 167
- Hardware and Architecture 100
- Signal Processing 77
- Computer Vision and Pattern Recognition 76
- Computer Networks and Communications 55
Countries citing papers authored by T. Takayanagi
This map shows the geographic impact of T. Takayanagi's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by T. Takayanagi with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites T. Takayanagi more than expected).
Fields of papers citing papers by T. Takayanagi
This network shows the impact of papers produced by T. Takayanagi. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by T. Takayanagi. The network helps show where T. Takayanagi may publish in the future.
Co-authorship network of co-authors of T. Takayanagi
This figure shows the co-authorship network connecting the top 25 collaborators of T. Takayanagi. A scholar is included among the top collaborators of T. Takayanagi based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with T. Takayanagi. T. Takayanagi is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 18 | |
| 2 | 21 | |
| 3 | 2 | |
| 4 | 10 | |
| 5 | 3 | |
| 6 | 3 | |
| 7 | 25 | |
| 8 | 0 | |
| 9 | 3 | |
| 10 | 0 | |
| 11 | 18 | |
| 12 | 14 | |
| 13 | 59 | |
| 14 | 68 | |
| 15 | 4 | |
| 16 | 9 | |
| 17 | 7 | |
| 18 | 1 | |
| 19 | A Circuit Design of 32KByte Integrated Cache Memory | 1 |
About T. Takayanagi
T. Takayanagi is a scholar working on Hardware and Architecture, Computer Networks and Communications and Electrical and Electronic Engineering, having authored 19 papers that have together received 266 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (11 papers), Parallel Computing and Optimization Techniques (7 papers) and Interconnection Networks and Systems (6 papers). The work is most often cited by research in Hardware and Architecture (100 citations), Signal Processing (77 citations) and Computer Vision and Pattern Recognition (76 citations). T. Takayanagi has collaborated with scholars based in Japan, United States and South Korea. Frequent co-authors include Tadahiro Kuroda, Hiroyuki Hara, Jinuk Luke Shin, M. Hamada, Kenji Ohmori, T. Furuyama, Nobuya Machida, T. Terazawa, Yoshinori Watanabe and Hiroki Nakamura. Their work appears in journals such as IEEE Journal of Solid-State Circuits.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.