M. Nagamatsu

682 total citations
18 papers, 459 citations indexed

About

M. Nagamatsu is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, M. Nagamatsu has authored 18 papers receiving a total of 459 indexed citations (citations by other indexed papers that have themselves been cited), including 15 papers in Electrical and Electronic Engineering, 9 papers in Hardware and Architecture and 5 papers in Computer Networks and Communications. Recurrent topics in M. Nagamatsu's work include Parallel Computing and Optimization Techniques (8 papers), Low-power high-performance VLSI design (7 papers) and Analog and Mixed-Signal Circuit Design (4 papers). M. Nagamatsu is often cited by papers focused on Parallel Computing and Optimization Techniques (8 papers), Low-power high-performance VLSI design (7 papers) and Analog and Mixed-Signal Circuit Design (4 papers). M. Nagamatsu collaborates with scholars based in Japan and United States. M. Nagamatsu's co-authors include Kumiko Kikuchi, N. Henmi, T. Okoshi, S. Tanaka, Toshinori Sato, K. Hatanaka, T. Noguchi, Koji Hirano, Y. Toyoshima and H. Hayashida and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, Journal of Lightwave Technology and Electronics Letters.

In The Last Decade

M. Nagamatsu

15 papers receiving 423 citations

Peers

Countries citing papers authored by M. Nagamatsu

Since Specialization

Citations

This map shows the geographic impact of M. Nagamatsu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by M. Nagamatsu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites M. Nagamatsu more than expected).

Fields of papers citing papers by M. Nagamatsu

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by M. Nagamatsu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by M. Nagamatsu. The network helps show where M. Nagamatsu may publish in the future.

Co-authorship network of co-authors of M. Nagamatsu

This figure shows the co-authorship network connecting the top 25 collaborators of M. Nagamatsu. A scholar is included among the top collaborators of M. Nagamatsu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with M. Nagamatsu. M. Nagamatsu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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18 of 18 papers shown

#	Work	Indexed citations
1	A 3.96μm, 124dB Dynamic Range, 6.2mW Stacked Digital Pixel Sensor with Monochrome and Near-Infrared Dual-Channel Global Shutter Capture 2023 ·Song Chen, (unknown), (unknown), (unknown), (unknown), Wei Gao, (unknown), Tsung-Hsun Tsai, K. Miyauchi, Isao Takayanagi, M. Nagamatsu, (unknown), K. Mori, (unknown), (unknown), (unknown), Hsin-Li Chen, (unknown), (unknown), (unknown)	1
2	A novel zero-overlap/enclosure metal interconnection technology for high density logic VLSIs 2002 ·H. Shibata, (unknown), M. Nagamatsu, (unknown), K. Maeguchi	0
3	Importance of CAD tools and methodologies in high speed CPU design 2002 ·(unknown), (unknown), (unknown), M. Nagamatsu, M. Suzuoki, (unknown)	3
4	A 150 MIPS/W CMOS RISC processor for PDA applications 2002 ·M. Nagamatsu, (unknown), (unknown), (unknown), Hiroaki Murakami, (unknown), Hironori Goto, (unknown), (unknown), (unknown), Atsushi Kawasumi, (unknown)	3
5	A 300 MIPS, 300 MFLOPS four-issue CMOS superscalar microprocessor 2002 ·(unknown), S. Tanaka, K. Sawada, M. Nagamatsu, (unknown), T. Takayanagi, (unknown), (unknown), Koji Miyamoto, Y. Hiruta, Ping‐Yu Hsu, Paul Rodman, (unknown), (unknown), (unknown), (unknown), (unknown)	0
6	Embedded memory design for a four issue superscaler RISC microprocessor 2002 ·T. Takayanagi, K. Sawada, T. Sakurai, (unknown), S. Tanaka, (unknown), M. Nagamatsu, (unknown), (unknown), (unknown), Ping‐Yu Hsu, Paul Rodman, (unknown), (unknown), (unknown), (unknown), (unknown)	0
7	Tabular editors for Geant4: Geant4 geometry editor and Geant4 physics editor 2000 ·Prepared for ·H. P. Yoshida, Tomoko Kodama, M. Nagamatsu, (unknown), (unknown), (unknown)	2
8	Importance of CAD tools and methodology in high speed CPU design 2000 ·(unknown), (unknown), (unknown), M. Nagamatsu, M. Suzuoki, (unknown)	3
9	Experience of prototyping Tcl/tk-based GUI for Geant4: An object-oriented Toolkit for simulation in high energy physics 1997 ·M. Nagamatsu, H. Uno, (unknown), Hajime Yoshida, Makoto Asai, (unknown), R. Hamatsu	1
10	Evaluation of architecture-level power estimation for CMOS RISC processors 1995 ·Toshinori Sato, (unknown), M. Nagamatsu, (unknown)	39
11	Power and performance simulator: ESP and its application for 100 MIPS/W class RISC design 1994 ·Toshinori Sato, M. Nagamatsu, (unknown)	35
12	A 320 MFLOPS CMOS floating-point processing unit for superscalar processors 1993 ·IEEE Journal of Solid-State Circuits ·(unknown), (unknown), (unknown), Toshiya Yoshida, M. Nagamatsu, (unknown), (unknown), K. Ueno	13
13	A 10 ns 5454 b parallel structured full array multiplier with 0.5 mu m CMOS technology 1991 ·IEEE Journal of Solid-State Circuits* ·(unknown), M. Nagamatsu, (unknown), S. Tanaka, Makoto Noda, Y. Toyoshima, Koh Hashimoto, H. Hayashida, K. Maeguchi	88
14	A 15-ns 3232-b CMOS multiplier with an improved parallel structure 1990 ·IEEE Journal of Solid-State Circuits* ·M. Nagamatsu, S. Tanaka, (unknown), Koji Hirano, T. Noguchi, K. Hatanaka	69
15	A 10 ns 54&times;54-bit parallel structured full array multiplier with 0.5 &mu;m CMOS technology 1990 ·(unknown), M. Nagamatsu, (unknown), S. Tanaka, Makoto Noda, Y. Toyoshima, Koh Hashimoto, H. Hayashida, K. Maeguchi	7
16	A 15 ns 32&times;32-bit CMOS multiplier with an improved parallel structure 1989 ·M. Nagamatsu, S. Tanaka, (unknown), T. Noguchi, K. Hatanaka	18
17	Degradation of bit-error rate in coherent optical communications due to spectral spread of the transmitter and the local oscillator 1984 ·Journal of Lightwave Technology ·Kumiko Kikuchi, T. Okoshi, M. Nagamatsu, N. Henmi	152
18	Bit-error rate of PSK heterodyne optical communication system and its degradation due to spectral spread of transmitter and local oscillator 1983 ·Electronics Letters ·Kumiko Kikuchi, T. Okoshi, M. Nagamatsu, N. Henmi	25

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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