E.M. Rudnick

2.0k total citations
67 papers, 1.3k citations indexed

About

E.M. Rudnick is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Control and Systems Engineering. According to data from OpenAlex, E.M. Rudnick has authored 67 papers receiving a total of 1.3k indexed citations (citations by other indexed papers that have themselves been cited), including 65 papers in Hardware and Architecture, 63 papers in Electrical and Electronic Engineering and 7 papers in Control and Systems Engineering. Recurrent topics in E.M. Rudnick's work include VLSI and Analog Circuit Testing (65 papers), Integrated Circuits and Semiconductor Failure Analysis (52 papers) and Radiation Effects in Electronics (27 papers). E.M. Rudnick is often cited by papers focused on VLSI and Analog Circuit Testing (65 papers), Integrated Circuits and Semiconductor Failure Analysis (52 papers) and Radiation Effects in Electronics (27 papers). E.M. Rudnick collaborates with scholars based in United States, Italy and Germany. E.M. Rudnick's co-authors include J.H. Patel, Michael S. Hsiao, T.M. Niermann, Pinaki Mazumder, G.S. Choi, Ravishankar K. Iyer, Vivek Chickermane, T. Bergfeld, W.K. Fuchs and Prithviraj Banerjee and has published in prestigious journals such as Journal of The Electrochemical Society, IEEE Transactions on Computers and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

E.M. Rudnick

64 papers receiving 1.2k citations

Peers

Countries citing papers authored by E.M. Rudnick

Since Specialization

Citations

This map shows the geographic impact of E.M. Rudnick's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by E.M. Rudnick with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites E.M. Rudnick more than expected).

Fields of papers citing papers by E.M. Rudnick

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by E.M. Rudnick. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by E.M. Rudnick. The network helps show where E.M. Rudnick may publish in the future.

Co-authorship network of co-authors of E.M. Rudnick

This figure shows the co-authorship network connecting the top 25 collaborators of E.M. Rudnick. A scholar is included among the top collaborators of E.M. Rudnick based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with E.M. Rudnick. E.M. Rudnick is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Title	Journal	Authors	Indexed citations
1	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits		I.N. Hajj, E.M. Rudnick et al.	12
2	A genetic approach to automatic bias generation for biased random instruction generation		Jongshin Shin, E.M. Rudnick et al.	27
3	Architectural-level fault simulation using symbolic data		E.M. Rudnick, J.H. Patel et al.	10
4	Automatic bias generation using pipeline instruction state coverage for biased random instruction generation		E.M. Rudnick, Magdy S. Abadir et al.	0
5	Application of simple genetic algorithms to sequential circuit test generation		E.M. Rudnick, John G. Holm et al.	35
6	Enhancing high-level control-flow for improved testability		E.M. Rudnick, J.H. Patel et al.	14
7	Automatic generation of diagnostic March tests		E.M. Rudnick et al.	15
8	Putting the squeeze on test sequences		E.M. Rudnick, J.H. Patel	4
9	On potential fault detection in sequential circuits		E.M. Rudnick, J.H. Patel et al.	2
10	Compact Test Generation Using a Frozen Clock Testing Strategy	Journal of information science and engineering	E.M. Rudnick, M. Abramovici	2
11	Peak power estimation of VLSI circuits: new peak power measures	IEEE Transactions on Very Large Scale Integration (VLSI) Systems	Michael S. Hsiao, E.M. Rudnick et al.	19
12	Parallel implementations		Shiwali Mohan, Pinaki Mazumder et al.	1
13	Fast static compaction algorithms for sequential circuit test vectors	IEEE Transactions on Computers	Michael S. Hsiao, E.M. Rudnick et al.	48
14	A diagnostic fault simulator for fast diagnosis of bridge faults		E.M. Rudnick et al.	4
15	Application of genetically engineered finite-state-machine sequences to sequential circuit ATPG	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems	Michael S. Hsiao, E.M. Rudnick et al.	14
16	Effects of delay models on peak power estimation of VLSI sequential circuits	International Conference on Computer Aided Design	Michael S. Hsiao, E.M. Rudnick et al.	26
17	Combining Deterministic and Genetic Approaches for Sequential Circuit Test Generation	Proceedings - ACM IEEE Design Automation Conference	E.M. Rudnick	3
18	Combining deterministic and genetic approaches for sequential circuit test generation		E.M. Rudnick, J.H. Patel	41
19	Simulation-Based Techniques for Sequential Circuit Testing	IDEALS (University of Illinois Urbana-Champaign)	E.M. Rudnick	7
20	An observability enhancement approach for improved testability and at-speed test	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems	E.M. Rudnick, Vivek Chickermane et al.	26

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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