Hsie-Chia Chang

1.6k total citations
100 papers, 1.2k citations indexed

About

Hsie-Chia Chang is a scholar working on Electrical and Electronic Engineering, Computer Networks and Communications and Artificial Intelligence. According to data from OpenAlex, Hsie-Chia Chang has authored 100 papers receiving a total of 1.2k indexed citations (citations by other indexed papers that have themselves been cited), including 68 papers in Electrical and Electronic Engineering, 67 papers in Computer Networks and Communications and 47 papers in Artificial Intelligence. Recurrent topics in Hsie-Chia Chang's work include Error Correcting Code Techniques (61 papers), Advanced Wireless Communication Techniques (54 papers) and Coding theory and cryptography (33 papers). Hsie-Chia Chang is often cited by papers focused on Error Correcting Code Techniques (61 papers), Advanced Wireless Communication Techniques (54 papers) and Coding theory and cryptography (33 papers). Hsie-Chia Chang collaborates with scholars based in Taiwan, United States and Switzerland. Hsie-Chia Chang's co-authors include Chen‐Yi Lee, Chih-Lung Chen, Po-Chun Liu, Chien-Ching Lin, C.B. Shung, Shyh‐Jye Jou, Yarsun Hsu, Chih-Hao Liu, Shu Lin and Kaili Lin and has published in prestigious journals such as SHILAP Revista de lepidopterología, IEEE Transactions on Signal Processing and IEEE Transactions on Communications.

In The Last Decade

Hsie-Chia Chang

95 papers receiving 1.1k citations

Peers

Countries citing papers authored by Hsie-Chia Chang

Since Specialization

Citations

This map shows the geographic impact of Hsie-Chia Chang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Hsie-Chia Chang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Hsie-Chia Chang more than expected).

Fields of papers citing papers by Hsie-Chia Chang

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Hsie-Chia Chang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Hsie-Chia Chang. The network helps show where Hsie-Chia Chang may publish in the future.

Co-authorship network of co-authors of Hsie-Chia Chang

This figure shows the co-authorship network connecting the top 25 collaborators of Hsie-Chia Chang. A scholar is included among the top collaborators of Hsie-Chia Chang based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Hsie-Chia Chang. Hsie-Chia Chang is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	GC-Like LDPC Code Construction and its NN-Aided Decoder Implementation 2024 ·SHILAP Revista de lepidopterología ·(unknown), (unknown), (unknown), Hsie-Chia Chang	1
2	F1: Striking the Balance Between Energy Efficiency & Flexibility: General-Purpose vs Special-Purpose ML Processors 2021 ·Archivio istituzionale della ricerca (Alma Mater Studiorum Università di Bologna) ·(unknown), (unknown), Luca Benini, Tanay Karnik, Hsie-Chia Chang	2
3	Scalable Globally-Coupled Low-Density Parity Check Codes 2018 ·(unknown), Hsie-Chia Chang, Shu Lin	8
4	An Improved DPA Countermeasure Based on Uniform Distribution Random Power Generator for IoT Applications 2017 ·IEEE Transactions on Circuits and Systems I Regular Papers ·(unknown), Chun-Yuan Yu, (unknown), Hsie-Chia Chang, Chen‐Yi Lee	6
5	An Efficient Decoder Architecture for Nonbinary LDPC Codes With Extended Min-Sum Algorithm 2016 ·IEEE Transactions on Circuits & Systems II Express Briefs ·(unknown), (unknown), Chih-Lung Chen, Hsie-Chia Chang, Chen‐Yi Lee	14
6	A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory 2015 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown), Chih-Lung Chen, Hsie-Chia Chang	31
7	A 3.46 Gb/s (9141,8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications 2015 ·(unknown), Chih-Lung Chen, (unknown), Hsie-Chia Chang, Chen‐Yi Lee	8
8	A 3.3V 15.6b 6.1pJ/0.02%RH with 10ms response humidity sensor for respiratory monitoring 2014 ·Kelvin Yi-Tse Lai, Yu-Tao Yang, (unknown), (unknown), (unknown), (unknown), Hsie-Chia Chang, Chen‐Yi Lee	4
9	A 3.40ms/GF(p(521)) and 2.77ms/GF(2(521)) DF-ECC Processor with Side-Channel Attack Resistance 2013 ·(unknown), (unknown), Hsie-Chia Chang, Chen‐Yi Lee	3
10	A 3.66Gb/s 275mW TB-LDPC-CC decoder chip for MIMO broadcasting communications 2013 ·Chih-Lung Chen, Yucheng Lan, Hsie-Chia Chang, Chen‐Yi Lee	5
11	An improved LT encoding scheme with extended chain lengths 2012 ·International Symposium on Information Theory and its Applications ·(unknown), Chih-Lung Chen, Hsie-Chia Chang	0
12	High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver 2011 ·IEEE Transactions on Circuits and Systems I Regular Papers ·(unknown), Hsie-Chia Chang	14
13	A long block length bch decoder for DVB-S2 application 2009 ·(unknown), (unknown), Chien-Ching Lin, Hsie-Chia Chang	8
14	A 11.5-Gbps LDPC decoder based on CP-PEG code construction 2009 ·Chih-Lung Chen, (unknown), Hsie-Chia Chang, Wai-Chi Fang, Chen‐Yi Lee	17
15	A Self-Compensation Fixed-Width Booth Multiplier and Its 128-point FFT Applications 2006 ·Hong‐Yi Huang, (unknown), Hsie-Chia Chang	23
16	Carry Estimation for Two's Complement Fixed-Width Multipliers 2006 ·(unknown), Hsie-Chia Chang, Chih‐Wei Liu	20
17	A 952MS/s Max-Log MAP Decoder Chip using Radix-4 × 4 ACS Architecture 2006 ·(unknown), (unknown), Chih-Lung Chen, Chien-Ching Lin, Hsie-Chia Chang	11
18	A 480Mb/s LDPC-COFDM-based UWB baseband transceiver 2005 ·(unknown), Chien-Ching Lin, Yu‐Wei Lin, Ching-Che Chung, Kaili Lin, (unknown), (unknown), Hsie-Chia Chang, Chen‐Yi Lee	23
19	A Low-Power Design for Reed–Solomon Decoders 2003 ·Journal of Circuits Systems and Computers ·Hsie-Chia Chang, Chen‐Yi Lee	0
20	A high speed Reed–Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm 2002 ·European Solid-State Circuits Conference ·Hsie-Chia Chang, Ching-Che Chung, Chien-Ching Lin, Chen‐Yi Lee	3

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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