J. Tierno

616 citations

27 papers · 462 · h-index 15

Impact in

Hardware and Architecture top 5%
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 10%
- Advancements in PLL and VCO Technologies
- Optical Network Technologies
- Radio Frequency Integrated Circuit Design
- Photonic and Optical Devices
- Semiconductor Lasers and Optical Devices
- Low-power high-performance VLSI design

Papers in

Electrical and Electronic Engineering 25
- Low-power high-performance VLSI design 10
- Advancements in PLL and VCO Technologies 9
- Photonic and Optical Devices 9
- Optical Network Technologies 7
- Radio Frequency Integrated Circuit Design 6
- Semiconductor Lasers and Optical Devices 6
Biomedical Engineering 7
- Analog and Mixed-Signal Circuit Design 6

Co-authors: P. Pepeljugoski (7 shared papers)J.D. Schaub (5 shared papers)S. Gowda (5 shared papers)Alexander Rylyakov (8 shared papers)Ali Hajimiri (4 shared papers)J. A. Kash (4 shared papers)Hui Wu (3 shared papers)Daniel J. Friedman (8 shared papers)
Journals: IBM Journal of Research and Development (2 papers)IEEE Journal of Solid-State Circuits (1 paper)Journal of Lightwave Technology (1 paper)IEEE Photonics Technology Letters (1 paper)IEEE Transactions on Circuits and Systems I Regular Papers (1 paper)
Partner nations: United States Germany Taiwan

In The Last Decade

J. Tierno

27 papers receiving 439 citations

Peers

Countries citing papers authored by J. Tierno

Since Specialization

Citations

This map shows the geographic impact of J. Tierno's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Tierno with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Tierno more than expected).

Fields of papers citing papers by J. Tierno

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Tierno. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Tierno. The network helps show where J. Tierno may publish in the future.

Co-authors

The 25 scholars most cited alongside J. Tierno, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with J. Tierno Line = papers co-authored together J. Tierno links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Showing the 20 most-cited of 27 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Integrated transversal equalizers in high-speed fiber-optic systems IEEE Journal of Solid-State Circuits ·Hui Wu, J. Tierno, P. Pepeljugoski, J.D. Schaub, S. Gowda, J. A. Kash, Ali Hajimiri	2003	104
2	Bang-bang digital PLLs at 11 and 20GHz with sub-200fs integrated jitter for high-speed serial communication applications Alexander Rylyakov, J. Tierno, H. Ainspan, Jean‐Olivier Plouchart, John F. Bulzacchelli, Zeynep Toprak-Deniz, Daniel J. Friedman	2009	51
3	Adaptive energy-management features of the IBM POWER7 chip IBM Journal of Research and Development ·Michael S. Floyd, M. Ware, Karthick Rajamani, Tilman Gloekler, Bishop Brock, Pradip Bose, Alper Buyuktosunoglu, (unknown), Birgit Schubert, B. Spruth, J. Tierno, Lorena Pesantez	2011	28
4	A 7-Tap transverse analog-FIR filter in 0.13μm CMOS for equalization of 10Gb/s fiber-optic data systems Scott Reynolds, P. Pepeljugoski, J.D. Schaub, J. Tierno, Donald Beisser	2005	23
5	Differential 4-tap and 7-tap transverse filters in SiGe for 10Gb/s multimode fiber optic link equalization Hui Wu, J. Tierno, P. Pepeljugoski, J.D. Schaub, S. Gowda, J. A. Kash, Ali Hajimiri	2003	23
6	An adaptively-pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 GigaHertz Montek Singh, J. Tierno, Alexander Rylyakov, S.V. Rylov, Steven M. Nowick	2004	20
7	Asynchronous parallel prefix computation IEEE Transactions on Computers ·Rajit Manohar, J. Tierno	1998	19
8	A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI Alexander Rylyakov, J. Tierno, George English, Daniel J. Friedman, M. Meghelli	2007	19
9	Improved performance of 10 Gb/s multimode fiber optic links using equalization P. Pepeljugoski, J.D. Schaub, J. Tierno, J. A. Kash, S. Gowda, B. Wilson, Hui Wu, Ali Hajimiri	2003	18
10	A 100-MIPS GaAs asynchronous microprocessor IEEE Design & Test of Computers ·J. Tierno, Alain J. Martin, Drazen Borkovic, Tak Kwan Lee	1994	17
11	Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion Shuyue Sun, F. Wang, Soner Yaldiz, X. Li, Larry Pileggi, Arun Natarajan, Mark Ferriss, Jean‐Olivier Plouchart, Bodhisatwa Sadhu, B. Parker, Alberto Valdes‐Garcia, Mihai Sanduleanu, J. Tierno, Daniel J. Friedman	2013	17
12	A Modular All-Digital PLL Architecture Enabling Both 1-to-2GHz and 24-to-32GHz Operation in 65nm CMOS Alexander Rylyakov, J. Tierno, Didem Turker, Jean‐Olivier Plouchart, H. Ainspan, Daniel J. Friedman	2008	17
13	A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI Yong Liu, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, L. Chang, J. Tierno, Daniel J. Friedman	2013	15
14	A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS IEEE Transactions on Circuits and Systems I Regular Papers ·Jean‐Olivier Plouchart, Mark Ferriss, Arun Natarajan, Alberto Valdes‐Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, B. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott Reynolds, J. Tierno, Daniel J. Friedman	2013	14
15	A 2.3 GSample/s 10-tap digital FIR filter for magnetic recording read channels S.V. Rylov, Alexander Rylyakov, J. Tierno, M. Immediato, Michael P. Beakes, Mohit Kapur, Paul Ampadu, D.J. Pearson	2002	14
16	A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) ·J. Tierno, Alexander Rylyakov, S.V. Rylov, Montek Singh, Paul Ampadu, Steven M. Nowick, M. Immediato, S. Gowda	2003	10
17	Indirect phase noise sensing for self-healing voltage controlled oscillators Soner Yaldiz, Vehbi Calayir, X. Li, Larry Pileggi, Arun Natarajan, Mark Ferriss, J. Tierno	2011	10
18	Performance of Simulated Annealing Algorithm in Equalized Multimode Fiber Links With Linear Equalizers Journal of Lightwave Technology ·P. Pepeljugoski, J. Tierno, Aleksandar Risteski, Scott Reynolds, Laurent Schares	2006	7
19	A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS Jean‐Olivier Plouchart, Mark Ferriss, Arun Natarajan, Alberto Valdes‐Garcia, Bodhisatwa Sadhu, Alexander Rylyakov, B. Parker, Michael P. Beakes, A. Babakani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott Reynolds, J. Tierno, Daniel J. Friedman	2012	6
20	Bringing optics inside the box: recent progress and future trends J. A. Kash, Christian Baks, S. Gowda, Lancelot Graham, Ali Hajimiri, C. Haymes, J. L. Jewell, D. Kucharski, Daniel M. Kuchta, Young Kwark, P. Pepeljugoski, J.D. Schaub, Christian Schuster, J. Tierno, Hualong Wu	2004	6

About J. Tierno

J. Tierno is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering, Hardware and Architecture, Signal Processing and Condensed Matter Physics, having authored 27 papers that have together received 462 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (10 papers), Advancements in PLL and VCO Technologies (9 papers), Photonic and Optical Devices (9 papers), Optical Network Technologies (7 papers), Analog and Mixed-Signal Circuit Design (6 papers), Radio Frequency Integrated Circuit Design (6 papers), Semiconductor Lasers and Optical Devices (6 papers) and Parallel Computing and Optimization Techniques (4 papers). The work is most often cited by research in Hardware and Architecture (125 citations), Electrical and Electronic Engineering (421 citations), Signal Processing (30 citations), Computer Networks and Communications (51 citations) and Biomedical Engineering (85 citations). J. Tierno has collaborated with scholars based in United States, Germany and Taiwan. Frequent co-authors include P. Pepeljugoski, J.D. Schaub, S. Gowda, Alexander Rylyakov, Ali Hajimiri, J. A. Kash, Hui Wu, Daniel J. Friedman, Jean‐Olivier Plouchart and Rajit Manohar. Their work appears in journals such as IBM Journal of Research and Development, IEEE Journal of Solid-State Circuits, Journal of Lightwave Technology, IEEE Photonics Technology Letters and IEEE Transactions on Circuits and Systems I Regular Papers.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact

J. Tierno

Impact in

Papers in i

In The Last Decade

J. Tierno

Peers

Countries citing papers authored by J. Tierno

Fields of papers citing papers by J. Tierno

All Works

About J. Tierno

Explore authors with similar magnitude of impact

Papers in