José Tierno

1.3k total citations
20 papers, 978 citations indexed

About

José Tierno is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Small Animals. According to data from OpenAlex, José Tierno has authored 20 papers receiving a total of 978 indexed citations (citations by other indexed papers that have themselves been cited), including 19 papers in Electrical and Electronic Engineering, 5 papers in Hardware and Architecture and 1 paper in Small Animals. Recurrent topics in José Tierno's work include Advancements in PLL and VCO Technologies (13 papers), Radio Frequency Integrated Circuit Design (9 papers) and Electromagnetic Compatibility and Noise Suppression (7 papers). José Tierno is often cited by papers focused on Advancements in PLL and VCO Technologies (13 papers), Radio Frequency Integrated Circuit Design (9 papers) and Electromagnetic Compatibility and Noise Suppression (7 papers). José Tierno collaborates with scholars based in United States. José Tierno's co-authors include Daniel J. Friedman, Alexander Rylyakov, Benjamin D. Parker, Alan J. Drake, Bishop Brock, Charles Lefurgy, Michael S. Floyd, Malcolm Allen-Ware, Bernard Brezzo and Leland Chang and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I Regular Papers and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

José Tierno

20 papers receiving 942 citations

Peers

José Tierno

EEE

CNC

CMN

Anh Tuan Singapore

Alexandre Valentian France

Lorena Anghel France

Tsung-Te Liu Taiwan

René Schüffny Germany

Tobias Gemmeke Germany

Joyce Kwong United States

Andrea Calimera Italy

Shuangchen Li China

Pi-Feng Chiu United States

Anh Tuan Singapore

José Tierno

506 ×0.6

EEE

163 ×0.6

73 ×0.4

70 ×0.6

CNC

119 ×1.1

CMN

Citations per year, relative to José Tierno José Tierno (= 1×) peers Anh Tuan

Countries citing papers authored by José Tierno

Since Specialization

Citations

This map shows the geographic impact of José Tierno's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by José Tierno with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites José Tierno more than expected).

Fields of papers citing papers by José Tierno

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by José Tierno. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by José Tierno. The network helps show where José Tierno may publish in the future.

Co-authorship network of co-authors of José Tierno

This figure shows the co-authorship network connecting the top 25 collaborators of José Tierno. A scholar is included among the top collaborators of José Tierno based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with José Tierno. José Tierno is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Dickson, Timothy O., Yong Liu, S.V. Rylov, et al.. (2015). A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. IEEE Journal of Solid-State Circuits. 50(8). 1917–1931. 24 indexed citations

Ferriss, Mark, Alexander Rylyakov, José Tierno, H. Ainspan, & Daniel J. Friedman. (2014). A 28 GHz Hybrid PLL in 32 nm SOI CMOS. IEEE Journal of Solid-State Circuits. 49(4). 1027–1035. 6 indexed citations

Sun, Shupeng, Fa Wang, Soner Yaldiz, et al.. (2014). Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. IEEE Transactions on Circuits and Systems I Regular Papers. 61(8). 2243–2252. 18 indexed citations

Lefurgy, Charles, Alan J. Drake, Michael S. Floyd, et al.. (2013). Active Guardband Management in Power7+ to Save Energy and Maintain Reliability. IEEE Micro. 33(4). 35–45. 44 indexed citations

Sadhu, Bodhisatwa, Mark Ferriss, Arun Natarajan, et al.. (2013). A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE Journal of Solid-State Circuits. 48(5). 1138–1150. 55 indexed citations

Ferriss, Mark, Jean‐Olivier Plouchart, Arun Natarajan, et al.. (2013). An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. IEEE Journal of Solid-State Circuits. 48(4). 996–1008. 40 indexed citations

Ferriss, Mark, Jean‐Olivier Plouchart, Arun Natarajan, et al.. (2012). An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS. 176–177. 5 indexed citations

Agrawal, Ankur, John F. Bulzacchelli, Timothy O. Dickson, et al.. (2012). A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS. IEEE Journal of Solid-State Circuits. 47(12). 3220–3231. 63 indexed citations

Sadhu, Bodhisatwa, Mark Ferriss, Jean‐Olivier Plouchart, et al.. (2012). A 21.8–27.5GHz PLL in 32nm SOI using Gm linearization to achieve −130dBc/Hz phase noise at 10MHz offset from a 22GHz carrier. 75–78. 6 indexed citations

10.

Asaad, Sameh, R. Bellofatto, Bernard Brezzo, et al.. (2012). A cycle-accurate, cycle-reproducible multi-FPGA system for accelerating multi-core processor simulation. 153–162. 40 indexed citations

11.

Agrawal, Ankur, John F. Bulzacchelli, Timothy O. Dickson, et al.. (2012). A 19Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45nm SOI CMOS. 134–136. 14 indexed citations

12.

Seo, Jae-sun, Bernard Brezzo, Yong Liu, et al.. (2011). A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. 1–4. 264 indexed citations

13.

Floyd, Michael S., Malcolm Allen-Ware, Karthick Rajamani, et al.. (2011). Introducing the Adaptive Energy Management Features of the Power7 Chip. IEEE Micro. 31(2). 60–75. 89 indexed citations

14.

Lefurgy, Charles, Alan J. Drake, Michael S. Floyd, et al.. (2011). Active management of timing guardband to save energy in POWER7. 1–11. 113 indexed citations

15.

Tierno, José, Alexander Rylyakov, Daniel J. Friedman, et al.. (2010). A DPLL-based per core variable frequency clock generator for an eight-core POWER7<sup>™</sup> microprocessor. 85–86. 25 indexed citations

16.

Singh, Montek, José Tierno, Alexander Rylyakov, S.V. Rylov, & Steven M. Nowick. (2009). An Adaptively Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 Gigahertz. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18(7). 1043–1056. 11 indexed citations

17.

Rylyakov, Alexander, et al.. (2008). A wide tuning range (1 GHz-to-15 GHz) fractional-N all-digital PLL in 45nm SOI. 431–434. 12 indexed citations

18.

Tierno, José, Alexander Rylyakov, & Daniel J. Friedman. (2008). A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI. IEEE Journal of Solid-State Circuits. 43(1). 42–51. 147 indexed citations

19.

Tierno, José. (1995). Efeito da osteotomia de Salter no crescimento do osso ilíaco do coelho. Revista Brasileira de Ortopedia (English Edition). 30. 1 indexed citations

20.

Tierno, José. (1993). Designing Asynchronous Circuits in Gallium Arsenide. CaltechAUTHORS (California Institute of Technology). 1 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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