Jared Zerbe

1.6k total citations
46 papers, 1.3k citations indexed

About

Jared Zerbe is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Jared Zerbe has authored 46 papers receiving a total of 1.3k indexed citations (citations by other indexed papers that have themselves been cited), including 45 papers in Electrical and Electronic Engineering, 11 papers in Hardware and Architecture and 9 papers in Biomedical Engineering. Recurrent topics in Jared Zerbe's work include Advancements in PLL and VCO Technologies (40 papers), Semiconductor Lasers and Optical Devices (13 papers) and Radio Frequency Integrated Circuit Design (12 papers). Jared Zerbe is often cited by papers focused on Advancements in PLL and VCO Technologies (40 papers), Semiconductor Lasers and Optical Devices (13 papers) and Radio Frequency Integrated Circuit Design (12 papers). Jared Zerbe collaborates with scholars based in United States, Canada and South Korea. Jared Zerbe's co-authors include Kevin Donnelly, C. Werner, Mark Horowitz, Vladimir Stojanović, B.W. Garlepp, A. Ho, G. Tsang, J. Wei, Brian Leibowitz and Ravi Kollipara and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Circuits and Systems I Regular Papers and IEEE Transactions on Advanced Packaging.

In The Last Decade

Jared Zerbe

45 papers receiving 1.2k citations

Peers

Countries citing papers authored by Jared Zerbe

Since Specialization

Citations

This map shows the geographic impact of Jared Zerbe's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Jared Zerbe with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Jared Zerbe more than expected).

Fields of papers citing papers by Jared Zerbe

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Jared Zerbe. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Jared Zerbe. The network helps show where Jared Zerbe may publish in the future.

Co-authorship network of co-authors of Jared Zerbe

This figure shows the co-authorship network connecting the top 25 collaborators of Jared Zerbe. A scholar is included among the top collaborators of Jared Zerbe based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Jared Zerbe. Jared Zerbe is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS 2012 ·Kambiz Kaviani, Masum Hossain, Meisam Honarvar Nazari, (unknown), Jihong Ren, Jared Zerbe	5
2	A 5.6Gb/s 2.4mW/Gb/s bidirectional link with 8ns power-on 2011 ·Jared Zerbe, (unknown), W.D. Dettloff, (unknown), William Stonecypher, (unknown), (unknown), (unknown), Jihong Ren, (unknown), Brian Leibowitz, (unknown), Anthony Chan Carusone, J.C. Eble	20
3	System design considerations for a 5Gb/s source-synchronous link with common-mode clocking 2011 ·Jihong Ren, Dan Oh, Ravi Kollipara, (unknown), (unknown), Jared Zerbe, (unknown)	1
4	Power-efficient I/O design considerations for high-bandwidth applications 2011 ·J.C. Eble, (unknown), Brian Leibowitz, Lei Luo, R. Palmer, John Wilson, Jared Zerbe, Amir Amirkhany, Nhat Nguyen	4
5	A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques 2011 ·IEEE Journal of Solid-State Circuits ·Jared Zerbe, (unknown), Lei Luo, William Stonecypher, W.D. Dettloff, J.C. Eble, (unknown), Jihong Ren, Brian Leibowitz, Michael Bucher, (unknown), (unknown), (unknown), Ravi Kollipara	17
6	A 5Gb/s link with clock edge matching and embedded common mode clock for low power interfaces 2010 ·Jared Zerbe, (unknown), Lei Luo, (unknown), W.D. Dettloff, J.C. Eble, (unknown), Jihong Ren, Brian Leibowitz, Michael Bucher, (unknown), (unknown)	1
7	Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric 2008 ·IEEE Journal of Solid-State Circuits ·E-Hung Chen, Jihong Ren, Brian Leibowitz, (unknown), (unknown), (unknown), (unknown), Vladimir Stojanović, Jared Zerbe, Chih-Kong Ken Yang	34
8	Accurate System Voltage and Timing Margin Simulation in High-Speed I/O System Designs 2008 ·IEEE Transactions on Advanced Packaging ·Kyung Suk Oh, (unknown), Sam Chang, (unknown), Jihong Ren, Chuck Yuan, Jared Zerbe, Vladimir Stojanović	37
9	Precursor ISI Reduction in High-Speed I/O 2007 ·Jihong Ren, Haechang Lee, (unknown), Brian Leibowitz, E-Hung Chen, Dan Oh, (unknown), Vladimir Stojanović, Chih-Kong Ken Yang, Jared Zerbe	17
10	BER-based Adaptation of I/O Link Equalizers 2007 ·E-Hung Chen, Jihong Ren, Jared Zerbe, Brian Leibowitz, Haechang Lee, Vladimir Stojanović, Chih-Kong Ken Yang	1
11	PLL On-Chip Jitter Measurement: Analysis and Design 2006 ·(unknown), Vladimir Stojanović, Jared Zerbe, C. Werner, (unknown), Borivoje Nikolić	7
12	Modeling, simulation, and design of a multi-mode 2-10 Gb/sec fully adaptive serial link system 2006 ·C. Werner, (unknown), A. Ho, (unknown), (unknown), B.W. Garlepp, William Stonecypher, (unknown), Ankur Bansal, Anant Agarwal, E. Alon, Vladimir Stojanović, Jared Zerbe	5
13	Autonomous Dual-Mode (PAM2/4) Serial Link Transceiver with Adaptive Equalization and Data Recovery 2005 ·Vladimir Stojanović, (unknown), Fred K. Chen, J. Wei, G. Tsang, (unknown), (unknown), Ravi Kollipara, C. Werner, Jared Zerbe, Mark Horowitz	6
14	Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery 2005 ·IEEE Journal of Solid-State Circuits ·Vladimir Stojanović, A. Ho, B.W. Garlepp, (unknown), J. Wei, G. Tsang, E. Alon, Ravi Kollipara, C. Werner, Jared Zerbe, Mark Horowitz	113
15	Transition-limiting codes for 4-PAM signaling in high speed serial links 2004 ·(unknown), William Stonecypher, Anant Agarwal, Jared Zerbe	3
16	Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell 2003 ·Jared Zerbe, C. Werner, Vladimir Stojanović, (unknown), J. Wei, G. Tsang, (unknown), William Stonecypher, A. Ho, T.P. Thrush, Ravi Kollipara, (unknown), Mark Horowitz, Kevin Donnelly	27
17	A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM 2002 ·(unknown), Kevin Donnelly, (unknown), Jared Zerbe, M. Johnson, Takashi Ishikawa	6
18	1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus 2001 ·IEEE Journal of Solid-State Circuits ·Jared Zerbe, (unknown), C. Werner, T.P. Thrush, (unknown), B.W. Garlepp, Kevin Donnelly	41
19	A 2Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receviers 2001 ·Medical Entomology and Zoology ·Jared Zerbe	2
20	A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM 1994 ·IEEE Journal of Solid-State Circuits ·(unknown), Kevin Donnelly, (unknown), Jared Zerbe, M. Johnson, Takashi Ishikawa	141

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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