Yohan Frans

1.7k total citations
53 papers, 1.2k citations indexed

About

Yohan Frans is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, Yohan Frans has authored 53 papers receiving a total of 1.2k indexed citations (citations by other indexed papers that have themselves been cited), including 52 papers in Electrical and Electronic Engineering, 14 papers in Biomedical Engineering and 13 papers in Hardware and Architecture. Recurrent topics in Yohan Frans's work include Advancements in PLL and VCO Technologies (40 papers), Radio Frequency Integrated Circuit Design (29 papers) and Analog and Mixed-Signal Circuit Design (13 papers). Yohan Frans is often cited by papers focused on Advancements in PLL and VCO Technologies (40 papers), Radio Frequency Integrated Circuit Design (29 papers) and Analog and Mixed-Signal Circuit Design (13 papers). Yohan Frans collaborates with scholars based in United States, Belgium and South Korea. Yohan Frans's co-authors include Ken Chang, Parag Upadhyaya, Jay Im, Hongtao Zhang, Lei Zhou, Brian Leibowitz, Toan Thang Pham, Geoff G. Z. Zhang, Mayank Raj and Hiva Hedayati and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Advanced Packaging and IEEE Solid-State Circuits Letters.

In The Last Decade

Yohan Frans

51 papers receiving 1.1k citations

Author Peers

Peers are selected by citation overlap in the author's most active subfields. citations · hero ref

Author						Papers	Cites
Yohan Frans	1.1k	298	158	91	16	53	1.2k
Ken Chang	1.0k 0.9×	298 1.0×	125 0.8×	71 0.8×	14 0.9×	60	1.1k
Alessandro Cevrero	805 0.7×	258 0.9×	99 0.6×	96 1.1×	15 0.9×	55	837
Parag Upadhyaya	911 0.8×	243 0.8×	89 0.6×	42 0.5×	22 1.4×	58	925
Mozhgan Mansuri	1.2k 1.1×	347 1.2×	186 1.2×	90 1.0×	36 2.3×	43	1.3k
R.A. Hadaway	750 0.7×	345 1.2×	113 0.7×	42 0.5×	21 1.3×	17	785
Stephan Henzler	613 0.5×	313 1.1×	119 0.8×	61 0.7×	17 1.1×	35	663
K.R. Lakshmikumar	947 0.8×	522 1.8×	128 0.8×	61 0.7×	32 2.0×	25	986
Massimo Alioto	736 0.7×	228 0.8×	137 0.9×	38 0.4×	14 0.9×	16	768
Eisse Mensink	859 0.8×	465 1.6×	97 0.6×	269 3.0×	13 0.8×	15	910
R. Farjad-Rad	882 0.8×	314 1.1×	115 0.7×	88 1.0×	14 0.9×	20	911

Countries citing papers authored by Yohan Frans

Since Specialization

Citations

This map shows the geographic impact of Yohan Frans's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yohan Frans with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yohan Frans more than expected).

Fields of papers citing papers by Yohan Frans

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yohan Frans. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yohan Frans. The network helps show where Yohan Frans may publish in the future.

Co-authorship network of co-authors of Yohan Frans

This figure shows the co-authorship network connecting the top 25 collaborators of Yohan Frans. A scholar is included among the top collaborators of Yohan Frans based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yohan Frans. Yohan Frans is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Raj, Mayank, Wenfeng Zhang, Ying Cao, et al.. (2023). A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies. 11–13. 13 indexed citations

Zhang, Wenfeng, Junho Cho, Yipeng Wang, et al.. (2021). A 1.24pJ/b 112Gb/s (870Gbps/mm) Transceiver for In-package Links in 7nm FinFET. 1–2. 5 indexed citations

Raj, Mayank, Yohan Frans, Ping-Chuan Chiang, et al.. (2020). Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. IEEE Journal of Solid-State Circuits. 55(4). 1086–1095. 40 indexed citations

Frans, Yohan. (2019). ADC-based Wireline Transceiver. 1–89.

Upadhyaya, Parag, Bob Verbruggen, Ying Cao, et al.. (2018). A 7.4-to-14GHz PLL with 54fs<inf>rms</inf> jitter in 16nm FinFET for integrated RF-data-converter SoCs. 378–380. 53 indexed citations

Chen, Stanley, Lei Zhou, Jay Im, et al.. (2018). A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET. 390–392. 42 indexed citations

Upadhyaya, Parag, Arianne Roldan, Wenfeng Zhang, et al.. (2018). A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET. IEEE Journal of Solid-State Circuits. 54(1). 18–28. 29 indexed citations

Carey, Declan, Ronan Casey, Hongtao Zhang, et al.. (2018). A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. 47–48. 16 indexed citations

Upadhyaya, Parag, et al.. (2017). Design techniques for 32.75Gb/s and 56Gb/s wireline transceivers in 16nm FinFET. 1–4. 3 indexed citations

10.

Im, Jay, Arianne Roldan, Ronan Casey, et al.. (2017). A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET. IEEE Journal of Solid-State Circuits. 52(12). 3486–3502. 47 indexed citations

11.

Frans, Yohan, Jaewook Shin, Lei Zhou, et al.. (2017). A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET. IEEE Journal of Solid-State Circuits. 52(4). 1101–1110. 127 indexed citations

12.

Raj, Mayank, et al.. (2017). A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET. C182–C183. 21 indexed citations

13.

Frans, Yohan, Hiva Hedayati, Jay Im, et al.. (2016). A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. 35 indexed citations

14.

Carey, Declan, Ronan Casey, Yohan Frans, et al.. (2016). A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET. 297–300. 4 indexed citations

15.

Upadhyaya, Parag, Jay Im, Junho Cho, et al.. (2016). A fully-adaptive wideband 0.5–32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology. 1–2. 10 indexed citations

16.

Chang, Ken, Jafar Savoj, Parag Upadhyaya, & Yohan Frans. (2014). Device aware high-speed transceiver design in planar and FinFet technologies. 18.1.1–18.1.4. 1 indexed citations

17.

Oh, Dan, et al.. (2012). Optimizing the timing center for high-speed parallel buses. 168–175. 3 indexed citations

18.

Frans, Yohan, et al.. (2011). Design challenges of low-power and high-speed memory interface in advanced CMOS technology. Symposium on VLSI Technology. 110–111.

19.

Palmer, R., John W. Poulton, Brian Leibowitz, et al.. (2009). A 4.3GB/s mobile memory interface with power-efficient bandwidth scaling. 45(4). 136–137. 16 indexed citations

20.

Oh, Dan, Sam Chang, Joong-Ho Kim, et al.. (2009). Design and characterization of a 12.8GB/s low power differential memory system for mobile applications. 33–36. 17 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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