Yohan Frans

1.7k total citations
53 papers, 1.2k citations indexed

About

Yohan Frans is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Hardware and Architecture. According to data from OpenAlex, Yohan Frans has authored 53 papers receiving a total of 1.2k indexed citations (citations by other indexed papers that have themselves been cited), including 52 papers in Electrical and Electronic Engineering, 14 papers in Biomedical Engineering and 13 papers in Hardware and Architecture. Recurrent topics in Yohan Frans's work include Advancements in PLL and VCO Technologies (40 papers), Radio Frequency Integrated Circuit Design (29 papers) and Analog and Mixed-Signal Circuit Design (13 papers). Yohan Frans is often cited by papers focused on Advancements in PLL and VCO Technologies (40 papers), Radio Frequency Integrated Circuit Design (29 papers) and Analog and Mixed-Signal Circuit Design (13 papers). Yohan Frans collaborates with scholars based in United States, Belgium and South Korea. Yohan Frans's co-authors include Ken Chang, Parag Upadhyaya, Jay Im, Lei Zhou, Hongtao Zhang, Toan Thang Pham, Brian Leibowitz, Geoff G. Z. Zhang, Arianne Roldan and Mayank Raj and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Advanced Packaging and IEEE Solid-State Circuits Letters.

In The Last Decade

Yohan Frans

51 papers receiving 1.1k citations

Peers

Countries citing papers authored by Yohan Frans

Since Specialization

Citations

This map shows the geographic impact of Yohan Frans's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yohan Frans with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yohan Frans more than expected).

Fields of papers citing papers by Yohan Frans

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yohan Frans. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yohan Frans. The network helps show where Yohan Frans may publish in the future.

Co-authorship network of co-authors of Yohan Frans

This figure shows the co-authorship network connecting the top 25 collaborators of Yohan Frans. A scholar is included among the top collaborators of Yohan Frans based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yohan Frans. Yohan Frans is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A O.96pJ/b 7 × 50Gb/s-per-Fiber WDM Receiver with Stacked 7nm CMOS and 45nm Silicon Photonic Dies 2023 ·Mayank Raj, (unknown), (unknown), (unknown), Wenfeng Zhang, Ying Cao, Jae Wook Kim, (unknown), (unknown), Yipeng Wang, (unknown), Winson Lin, Jay Im, (unknown), (unknown), Parag Upadhyaya, Yohan Frans	13
2	A 1.24-pJ/b 112-Gb/s (870 Gb/s/Mm) Transceiver for In-Package Links in 7-nm FinFET 2022 ·IEEE Journal of Solid-State Circuits ·(unknown), Wenfeng Zhang, Junho Cho, (unknown), Yipeng Wang, Ying Cao, (unknown), (unknown), Winson Lin, Daniel Wu, (unknown), Parag Upadhyaya, Yohan Frans	17
3	Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET 2020 ·IEEE Journal of Solid-State Circuits ·Mayank Raj, Yohan Frans, Ping-Chuan Chiang, (unknown), (unknown), Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, (unknown), (unknown), Ken Chang	40
4	ADC-based Wireline Transceiver 2019 ·Yohan Frans	0
5	A 7.4-to-14GHz PLL with 54fs<inf>rms</inf> jitter in 16nm FinFET for integrated RF-data-converter SoCs 2018 ·(unknown), (unknown), Parag Upadhyaya, Bob Verbruggen, Ying Cao, (unknown), (unknown), Brendan Farley, Yohan Frans, Ken Chang	53
6	A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET 2018 ·Stanley Chen, Lei Zhou, (unknown), Jay Im, (unknown), (unknown), Mayank Raj, Jaewook Shin, Yohan Frans, Ken Chang	42
7	A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET 2018 ·IEEE Journal of Solid-State Circuits ·Parag Upadhyaya, (unknown), (unknown), (unknown), Arianne Roldan, Wenfeng Zhang, (unknown), Toan Thang Pham, (unknown), Winson Lin, Hongtao Zhang, (unknown), (unknown), Geoff G. Z. Zhang, Yohan Frans, Ken Chang	29
8	A 126mW 56Gb/s NRZ wireline transceiver for synchronous short-reach applications in 16nm FinFET 2018 ·(unknown), Declan Carey, (unknown), Ronan Casey, (unknown), (unknown), Mayank Raj, (unknown), Hongtao Zhang, Arianne Roldan, (unknown), Ping-Chuan Chiang, (unknown), (unknown), Yohan Frans, Ken Chang	27
9	Design techniques for 32.75Gb/s and 56Gb/s wireline transceivers in 16nm FinFET 2017 ·(unknown), Parag Upadhyaya, Jay Im, Stanley Chen, Yohan Frans, Ken Chang	3
10	A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET 2017 ·IEEE Journal of Solid-State Circuits ·Jay Im, (unknown), Arianne Roldan, Ronan Casey, Stanley Chen, (unknown), (unknown), (unknown), (unknown), Lei Zhou, (unknown), Jaeduk Han, Sen Lin, Parag Upadhyaya, (unknown), Yohan Frans, Ken Chang	47
11	A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET 2017 ·IEEE Journal of Solid-State Circuits ·Yohan Frans, Jaewook Shin, Lei Zhou, Parag Upadhyaya, Jay Im, (unknown), (unknown), Hiva Hedayati, Toan Thang Pham, (unknown), (unknown), Geoff G. Z. Zhang, Hongtao Zhang, Ken Chang	127
12	A 164fsrms 9-to-18GHz sampling phase detector based PLL with in-band noise suppression and robust frequency acquisition in 16nm FinFET 2017 ·Mayank Raj, (unknown), (unknown), Parag Upadhyaya, Yohan Frans, Ken Chang	21
13	A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET 2016 ·(unknown), (unknown), Declan Carey, Ronan Casey, (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), Yohan Frans, Jay Im, Parag Upadhyaya, Wenfeng Zhang, Winson Lin, (unknown), Ken Chang	4
14	A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET 2016 ·IEEE Journal of Solid-State Circuits ·Yohan Frans, (unknown), Hiva Hedayati, (unknown), (unknown), Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang	23
15	Crosstalk associated with solder ball and/or cutout-hole on the power/ground planes/nets 2016 ·Daniel Wu, Geoff G. Z. Zhang, Yohan Frans, (unknown), (unknown), (unknown), Ken Chang	1
16	Device aware high-speed transceiver design in planar and FinFet technologies 2014 ·Ken Chang, Jafar Savoj, Parag Upadhyaya, Yohan Frans	1
17	Optimizing the timing center for high-speed parallel buses 2012 ·Dan Oh, (unknown), (unknown), Yohan Frans, (unknown)	3
18	Design challenges of low-power and high-speed memory interface in advanced CMOS technology 2011 ·Symposium on VLSI Technology ·Yohan Frans, (unknown), Nhat Nguyen, Sunil Bhardwaj, Gary Bronner	0
19	A 4.3GB/s mobile memory interface with power-efficient bandwidth scaling 2009 ·R. Palmer, John W. Poulton, Brian Leibowitz, Yohan Frans, Simon Li, Andrew M. Fuller, John Eyles, John Wilson, Marko Aleksic, (unknown), Michael Bucher, Nhat Nguyen	16
20	Design and characterization of a 12.8GB/s low power differential memory system for mobile applications 2009 ·Dan Oh, Sam Chang, (unknown), Joong-Ho Kim, (unknown), Ming Li, (unknown), Brian Leibowitz, Yohan Frans, Nhat Nguyen	17

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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