Ching-Che Chung

1.3k total citations
85 papers, 937 citations indexed

About

Ching-Che Chung is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Computer Networks and Communications. According to data from OpenAlex, Ching-Che Chung has authored 85 papers receiving a total of 937 indexed citations (citations by other indexed papers that have themselves been cited), including 69 papers in Electrical and Electronic Engineering, 47 papers in Biomedical Engineering and 16 papers in Computer Networks and Communications. Recurrent topics in Ching-Che Chung's work include Advancements in PLL and VCO Technologies (50 papers), Analog and Mixed-Signal Circuit Design (39 papers) and Radio Frequency Integrated Circuit Design (29 papers). Ching-Che Chung is often cited by papers focused on Advancements in PLL and VCO Technologies (50 papers), Analog and Mixed-Signal Circuit Design (39 papers) and Radio Frequency Integrated Circuit Design (29 papers). Ching-Che Chung collaborates with scholars based in Taiwan, India and China. Ching-Che Chung's co-authors include Chen‐Yi Lee, Chih‐Yu Lin, Changjun Li, Chia‐Jung Yu, Hsie-Chia Chang, Kaili Lin, Chien-Ching Lin, Yu-Hsin Wang, Yu‐Wei Lin and Chen‐Ming Chang and has published in prestigious journals such as Applied Physics Letters, Sensors and IEEE Journal of Solid-State Circuits.

In The Last Decade

Ching-Che Chung

77 papers receiving 879 citations

Peers

Countries citing papers authored by Ching-Che Chung

Since Specialization

Citations

This map shows the geographic impact of Ching-Che Chung's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ching-Che Chung with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ching-Che Chung more than expected).

Fields of papers citing papers by Ching-Che Chung

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ching-Che Chung. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ching-Che Chung. The network helps show where Ching-Che Chung may publish in the future.

Co-authorship network of co-authors of Ching-Che Chung

This figure shows the co-authorship network connecting the top 25 collaborators of Ching-Che Chung. A scholar is included among the top collaborators of Ching-Che Chung based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ching-Che Chung. Ching-Che Chung is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Implementation of Lightweight Convolutional Neural Networks with an Early Exit Mechanism Utilizing 40 nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles 2024 ·Sensors ·(unknown), Chen‐Ming Chang, Ching-Che Chung	3
2	A One-Dimensional Depthwise Separable Convolutional Neural Network for Bearing Fault Diagnosis Implemented on FPGA 2024 ·Sensors ·(unknown), Hao Chen, Ching-Che Chung	0
3	A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery 2023 ·Sensors ·(unknown), (unknown), Ching-Che Chung	0
4	CNN Hardware Accelerator for Real-Time Bearing Fault Diagnosis 2023 ·Sensors ·Ching-Che Chung, (unknown), (unknown)	6
5	A Binary Weight Convolutional Neural Network Hardware Accelerator for Analysis Faults of the CNC Machinery on FPGA 2023 ·Ching-Che Chung, (unknown), (unknown), Chen‐Ming Chang	4
6	Using Quantization-Aware Training Technique with Post-Training Fine-Tuning Quantization to Implement a MobileNet Hardware Accelerator 2020 ·Ching-Che Chung, Wei‐Ting Chen, (unknown)	5
7	Design of a DBN Hardware Accelerator for Handwritten Digit Recognitions 2019 ·Ching-Che Chung, (unknown), (unknown)	1
8	An FPGA-Based Transceiver for Human Body Channel Communication Using Walsh Codes 2018 ·Ching-Che Chung, (unknown), (unknown)	6
9	A reference-less all-digital transceiver for human body channel communication 2017 ·Ching-Che Chung, (unknown), (unknown)	3
10	An all-digital voltage sensor for static voltage drop measurements 2016 ·Ching-Che Chung, (unknown)	4
11	A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling 2015 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Ching-Che Chung, (unknown), (unknown)	32
12	An all-digital phase-locked loop compiler with liberty timing files 2014 ·Ching-Che Chung, (unknown), (unknown)	5
13	A referenceless all-digital fast frequency acquisition full-rate CDR circuit for USB 2.0 in 65nm CMOS technology 2011 ·Ching-Che Chung, (unknown)	4
14	Fast-lock all-digital DLL and digitally-controlled phase shifter for DDR controller applications 2010 ·IEICE Electronics Express ·(unknown), Ching-Che Chung, Chen‐Yi Lee	5
15	An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications 2007 ·IEEE Transactions on Circuits & Systems II Express Briefs ·(unknown), Ching-Che Chung, Chen‐Yi Lee	74
16	A Fast-Lock-In ADPLL with High-Resolution and Low-Power DCO for SoC Applications 2006 ·(unknown), Ching-Che Chung, Chen‐Yi Lee	7
17	A 480Mb/s LDPC-COFDM-based UWB baseband transceiver 2005 ·(unknown), Chien-Ching Lin, Yu‐Wei Lin, Ching-Che Chung, Kaili Lin, (unknown), (unknown), Hsie-Chia Chang, Chen‐Yi Lee	23
18	A novel digitally-controlled varactor for portable delay cell design 2004 ·IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences ·(unknown), Ching-Che Chung, (unknown)	3
19	A New DLL-Based Approach for All-Digital Multiphase Clock Generation 2004 ·IEEE Journal of Solid-State Circuits ·Ching-Che Chung, Chen‐Yi Lee	51
20	A high speed Reed–Solomon decoder chip using inversionless decomposed architecture for Euclidean algorithm 2002 ·European Solid-State Circuits Conference ·Hsie-Chia Chang, Ching-Che Chung, Chien-Ching Lin, Chen‐Yi Lee	3

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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