M. Johnson

907 total citations
17 papers, 658 citations indexed

About

M. Johnson is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, M. Johnson has authored 17 papers receiving a total of 658 indexed citations (citations by other indexed papers that have themselves been cited), including 15 papers in Electrical and Electronic Engineering, 5 papers in Hardware and Architecture and 5 papers in Biomedical Engineering. Recurrent topics in M. Johnson's work include Low-power high-performance VLSI design (7 papers), Advancements in PLL and VCO Technologies (6 papers) and Advancements in Semiconductor Devices and Circuit Design (5 papers). M. Johnson is often cited by papers focused on Low-power high-performance VLSI design (7 papers), Advancements in PLL and VCO Technologies (6 papers) and Advancements in Semiconductor Devices and Circuit Design (5 papers). M. Johnson collaborates with scholars based in United States and Japan. M. Johnson's co-authors include Mark Horowitz, Michael D. Smith, Michael D. Smith, Jared Zerbe, Takashi Ishikawa, Kevin Donnelly, H. Partovi, D. Draper, J. Wei and W. C. Bowman and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, ACM SIGARCH Computer Architecture News and Defense Technical Information Center (DTIC).

In The Last Decade

M. Johnson

14 papers receiving 578 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
M. Johnson United States	10	497	274	245	182	27	17	658
J. Eno United States	7	638 1.3×	503 1.8×	179 0.7×	261 1.4×	28 1.0×	9	847
B.M. Gordon United Kingdom	4	446 0.9×	129 0.5×	165 0.7×	72 0.4×	23 0.9×	7	511
William J. Bowhill United States	7	800 1.6×	426 1.6×	109 0.4×	169 0.9×	23 0.9×	12	923
D. Murray United States	3	372 0.7×	334 1.2×	105 0.4×	194 1.1×	18 0.7×	4	531
D. Dobberpuhl United States	5	411 0.8×	346 1.3×	121 0.5×	193 1.1×	17 0.6×	8	567
Fumihiko Sano Japan	8	629 1.3×	183 0.7×	195 0.8×	76 0.4×	22 0.8×	12	721
Nasser Kurd United States	12	797 1.6×	393 1.4×	160 0.7×	166 0.9×	17 0.6×	30	889
Richard T. Witek United States	6	424 0.9×	406 1.5×	114 0.5×	248 1.4×	25 0.9×	13	632
David M. Bull United Kingdom	8	525 1.1×	275 1.0×	77 0.3×	60 0.3×	22 0.8×	12	577
Yiorgos Tsiatouhas Greece	11	603 1.2×	323 1.2×	85 0.3×	26 0.1×	14 0.5×	113	631

Countries citing papers authored by M. Johnson

Since Specialization

Citations

This map shows the geographic impact of M. Johnson's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by M. Johnson with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites M. Johnson more than expected).

Fields of papers citing papers by M. Johnson

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by M. Johnson. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by M. Johnson. The network helps show where M. Johnson may publish in the future.

Co-authorship network of co-authors of M. Johnson

This figure shows the co-authorship network connecting the top 25 collaborators of M. Johnson. A scholar is included among the top collaborators of M. Johnson based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with M. Johnson. M. Johnson is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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17 of 17 papers shown

Barner, J. B., A. Cavus, J. Uyeda, et al.. (2008). A mixed HEMT-HBT MMIC technology using MBE regrowth. 1067–1070.

Donnelly, Kevin, Samir Patel, Brian Lau, et al.. (2002). A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC. 290–291,.

Donnelly, Kevin, et al.. (2002). A 2.5 V delay-locked loop for an 18 Mb 500 MB/s DRAM. 300–301. 6 indexed citations

Draper, D., et al.. (2002). An X86 microprocessor with multimedia extensions. 172–173,. 8 indexed citations

Draper, D., et al.. (1997). Circuit techniques in a 266-MHz MMX-enabled processor. IEEE Journal of Solid-State Circuits. 32(11). 1650–1664. 27 indexed citations

Donnelly, Kevin, Jun Kim, Ching-Chao Huang, et al.. (1996). A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC. IEEE Journal of Solid-State Circuits. 31(12). 1995–2003. 11 indexed citations

Donnelly, Kevin, et al.. (1994). A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM. IEEE Journal of Solid-State Circuits. 29(12). 1491–1496. 141 indexed citations

Johnson, M.. (1993). An input-free V/sub T/ extractor circuit using a two-transistor differential amplifier. IEEE Journal of Solid-State Circuits. 28(6). 704–705. 38 indexed citations

Horowitz, Mark, et al.. (1990). A 3.5 ns, 1 Watt, ECL register file. 68–69. 6 indexed citations

10.

Bowman, W. C., et al.. (1990). A high density board mounted power module for distributed powering architectures. 43–54. 8 indexed citations

11.

Smith, Michael D., M. Johnson, & Mark Horowitz. (1989). Limits on multiple instruction issue. ACM SIGARCH Computer Architecture News. 17(2). 290–302. 101 indexed citations

12.

Smith, Michael D., M. Johnson, & Mark Horowitz. (1989). Limits on multiple instruction issue. 290–302. 83 indexed citations

13.

Johnson, M.. (1988). A symmetric CMOS NOR gate for high-speed applications. IEEE Journal of Solid-State Circuits. 23(5). 1233–1236. 25 indexed citations

14.

Johnson, M., et al.. (1988). A variable delay line PLL for CPU-coprocessor synchronization. IEEE Journal of Solid-State Circuits. 23(5). 1218–1223. 184 indexed citations

15.

Johnson, M., et al.. (1985). A 1-Mbit CMOS dynamic RAM with a divided bitline matrix architecture. IEEE Journal of Solid-State Circuits. 20(5). 894–902. 9 indexed citations

16.

Johnson, M., et al.. (1985). A 1Mb CMOS DRAM with a divided bitline matrix architecture. 242–243. 10 indexed citations

17.

Johnson, M.. (1982). Efficient modeling for short channel MOS circuit simulation. Defense Technical Information Center (DTIC). 3. 1 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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