W.D. Dettloff

534 total citations
15 papers, 370 citations indexed

About

W.D. Dettloff is a scholar working on Electrical and Electronic Engineering, Artificial Intelligence and Hardware and Architecture. According to data from OpenAlex, W.D. Dettloff has authored 15 papers receiving a total of 370 indexed citations (citations by other indexed papers that have themselves been cited), including 8 papers in Electrical and Electronic Engineering, 6 papers in Artificial Intelligence and 4 papers in Hardware and Architecture. Recurrent topics in W.D. Dettloff's work include Advancements in PLL and VCO Technologies (7 papers), Fuzzy Logic and Control Systems (5 papers) and Neural Networks and Applications (4 papers). W.D. Dettloff is often cited by papers focused on Advancements in PLL and VCO Technologies (7 papers), Fuzzy Logic and Control Systems (5 papers) and Neural Networks and Applications (4 papers). W.D. Dettloff collaborates with scholars based in United States, United Kingdom and Canada. W.D. Dettloff's co-authors include Hiroyuki Watanabe, J.C. Eble, Lei Luo, Michael Bucher, Brian Leibowitz, Jared Zerbe, B W Erickson, Jihong Ren, Carl White and William Stonecypher and has published in prestigious journals such as IEEE Journal of Solid-State Circuits and NASA STI/Recon Technical Report N.

In The Last Decade

W.D. Dettloff

15 papers receiving 336 citations

Peers

Countries citing papers authored by W.D. Dettloff

Since Specialization

Citations

This map shows the geographic impact of W.D. Dettloff's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by W.D. Dettloff with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites W.D. Dettloff more than expected).

Fields of papers citing papers by W.D. Dettloff

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by W.D. Dettloff. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by W.D. Dettloff. The network helps show where W.D. Dettloff may publish in the future.

Co-authorship network of co-authors of W.D. Dettloff

This figure shows the co-authorship network connecting the top 25 collaborators of W.D. Dettloff. A scholar is included among the top collaborators of W.D. Dettloff based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with W.D. Dettloff. W.D. Dettloff is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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15 of 15 papers shown

#	Work	Indexed citations
1	A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems 2013 ·IEEE Journal of Solid-State Circuits ·Michael Bucher, Ravi Kollipara, (unknown), (unknown), (unknown), (unknown), Kambiz Kaviani, (unknown), (unknown), W.D. Dettloff, (unknown), (unknown), Yi Lu, (unknown), (unknown), J.C. Eble, (unknown), Lei Luo	24
2	A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-fly rate switching 2012 ·Masum Hossain, Kambiz Kaviani, (unknown), (unknown), W.D. Dettloff, (unknown), (unknown), (unknown), J.C. Eble, Jared Zerbe	3
3	A 5.6Gb/s 2.4mW/Gb/s bidirectional link with 8ns power-on 2011 ·Jared Zerbe, (unknown), W.D. Dettloff, (unknown), William Stonecypher, (unknown), (unknown), (unknown), Jihong Ren, (unknown), Brian Leibowitz, (unknown), Anthony Chan Carusone, J.C. Eble	20
4	A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques 2011 ·IEEE Journal of Solid-State Circuits ·Jared Zerbe, (unknown), Lei Luo, William Stonecypher, W.D. Dettloff, J.C. Eble, (unknown), Jihong Ren, Brian Leibowitz, Michael Bucher, (unknown), (unknown), (unknown), Ravi Kollipara	17
5	A 5Gb/s link with clock edge matching and embedded common mode clock for low power interfaces 2010 ·Jared Zerbe, (unknown), Lei Luo, (unknown), W.D. Dettloff, J.C. Eble, (unknown), Jihong Ren, Brian Leibowitz, Michael Bucher, (unknown), (unknown)	1
6	A 32mW 7.4Gb/s protocol-agile source-series-terminated transmitter in 45nm CMOS SOI 2010 ·W.D. Dettloff, J.C. Eble, Lei Luo, (unknown), (unknown), (unknown), (unknown)	41
7	The Omnitest system: a no-generate, no-compile, interactive test methodology 2003 ·W.D. Dettloff, (unknown)	1
8	A fuzzy logic controller with reconfigurable, cascadable architecture 2003 ·W.D. Dettloff, (unknown), Hiroyuki Watanabe	1
9	A parallel processor ASIC for real time pattern recognition 2002 ·Mahmoud Mostafavi, (unknown), W.D. Dettloff	1
10	BioSCAN: a VLSI-based system for biosequence analysis 2002 ·Carl White, (unknown), (unknown), Johanna W. Lampe, B W Erickson, W.D. Dettloff, (unknown), Stephen F. Altschul	14
11	VLSI fuzzy chip and inference accelerator board systems 2002 ·Hiroyuki Watanabe, (unknown), W.D. Dettloff, (unknown)	19
12	A 50MHz 1.5M Transistor ASIC For Biosequence Analysis 1991 ·W.D. Dettloff, Raj Kumar Singh, Carl White, B W Erickson	4
13	A VLSI fuzzy logic controller with reconfigurable, cascadable architecture 1990 ·IEEE Journal of Solid-State Circuits ·Hiroyuki Watanabe, W.D. Dettloff, (unknown)	190
14	A VLSI fuzzy logic inference engine for real-time process control 1989 ·W.D. Dettloff, (unknown)	25
15	Fuzzy Logic Inference Processor for Real Time Control: A Second Generation Full Custom Design, 1986 ·NASA STI/Recon Technical Report N ·Hiroyuki Watanabe, W.D. Dettloff	9

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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