Ken Chang

1.5k total citations
60 papers, 1.1k citations indexed

About

Ken Chang is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Ken Chang has authored 60 papers receiving a total of 1.1k indexed citations (citations by other indexed papers that have themselves been cited), including 59 papers in Electrical and Electronic Engineering, 16 papers in Hardware and Architecture and 14 papers in Biomedical Engineering. Recurrent topics in Ken Chang's work include Advancements in PLL and VCO Technologies (47 papers), Radio Frequency Integrated Circuit Design (33 papers) and VLSI and Analog Circuit Testing (15 papers). Ken Chang is often cited by papers focused on Advancements in PLL and VCO Technologies (47 papers), Radio Frequency Integrated Circuit Design (33 papers) and VLSI and Analog Circuit Testing (15 papers). Ken Chang collaborates with scholars based in United States, South Korea and Belgium. Ken Chang's co-authors include Yohan Frans, Parag Upadhyaya, Jay Im, Geoff G. Z. Zhang, Hongtao Zhang, Lei Zhou, Stanley Chen, Toan Thang Pham, Arianne Roldan and Hiva Hedayati and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Advanced Packaging and IEEE Solid-State Circuits Magazine.

In The Last Decade

Ken Chang

56 papers receiving 1.1k citations

Author Peers

Peers are selected by citation overlap in the author's most active subfields. citations · hero ref

Author Last Decade Papers Cites
Ken Chang 1.0k 298 125 71 44 60 1.1k
Ching-Che Chung 827 0.8× 503 1.7× 115 0.9× 137 1.9× 19 0.4× 85 937
Nianxiong Tan 487 0.5× 405 1.4× 46 0.4× 71 1.0× 26 0.6× 52 558
R. Roovers 763 0.7× 438 1.5× 56 0.4× 82 1.2× 9 0.2× 40 835
R. Fernández 444 0.4× 395 1.3× 33 0.3× 46 0.6× 13 0.3× 71 539
G. Taylor 719 0.7× 229 0.8× 188 1.5× 54 0.8× 9 0.2× 53 788
Nicola Da Dalt 882 0.8× 359 1.2× 48 0.4× 44 0.6× 16 0.4× 36 929
Young-Hyun Jun 587 0.6× 176 0.6× 111 0.9× 129 1.8× 11 0.3× 60 667
Randy Mooney 1.1k 1.0× 231 0.8× 252 2.0× 102 1.4× 9 0.2× 31 1.1k
Mike Shuo‐Wei Chen 933 0.9× 514 1.7× 87 0.7× 35 0.5× 10 0.2× 83 997
Mozhgan Mansuri 1.2k 1.2× 347 1.2× 186 1.5× 90 1.3× 7 0.2× 43 1.3k

Countries citing papers authored by Ken Chang

Since Specialization
Citations

This map shows the geographic impact of Ken Chang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ken Chang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ken Chang more than expected).

Fields of papers citing papers by Ken Chang

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ken Chang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ken Chang. The network helps show where Ken Chang may publish in the future.

Co-authorship network of co-authors of Ken Chang

This figure shows the co-authorship network connecting the top 25 collaborators of Ken Chang. A scholar is included among the top collaborators of Ken Chang based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ken Chang. Ken Chang is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Zhang, Xin, et al.. (2025). A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring. IEEE Journal of Solid-State Circuits. 60(4). 1289–1298. 1 indexed citations
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Raj, Mayank, Yohan Frans, Ping-Chuan Chiang, et al.. (2020). Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET. IEEE Journal of Solid-State Circuits. 55(4). 1086–1095. 40 indexed citations
5.
Upadhyaya, Parag, Bob Verbruggen, Ying Cao, et al.. (2018). A 7.4-to-14GHz PLL with 54fs<inf>rms</inf> jitter in 16nm FinFET for integrated RF-data-converter SoCs. 378–380. 53 indexed citations
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Upadhyaya, Parag, Arianne Roldan, Wenfeng Zhang, et al.. (2018). A Fully Adaptive 19–58-Gb/s PAM-4 and 9.5–29-Gb/s NRZ Wireline Transceiver With Configurable ADC in 16-nm FinFET. IEEE Journal of Solid-State Circuits. 54(1). 18–28. 29 indexed citations
8.
Upadhyaya, Parag, et al.. (2017). Design techniques for 32.75Gb/s and 56Gb/s wireline transceivers in 16nm FinFET. 1–4. 3 indexed citations
9.
Im, Jay, Arianne Roldan, Ronan Casey, et al.. (2017). A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET. IEEE Journal of Solid-State Circuits. 52(12). 3486–3502. 47 indexed citations
10.
Frans, Yohan, Jaewook Shin, Lei Zhou, et al.. (2017). A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET. IEEE Journal of Solid-State Circuits. 52(4). 1101–1110. 127 indexed citations
11.
Frans, Yohan, Hiva Hedayati, Jay Im, et al.. (2016). A 56Gb/s PAM4 wireline transceiver using a 32-way time-interleaved SAR ADC in 16nm FinFET. 35 indexed citations
12.
Carey, Declan, Ronan Casey, Yohan Frans, et al.. (2016). A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET. 297–300. 4 indexed citations
13.
Upadhyaya, Parag, Jay Im, Junho Cho, et al.. (2016). A fully-adaptive wideband 0.5–32.75Gb/s FPGA transceiver in 16nm FinFET CMOS technology. 1–2. 10 indexed citations
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Chang, Ken, Frank O’Mahony, Elad Alon, et al.. (2015). F6: I/O design at 25Gb/s and beyond: Enabling the future communication infrastructure for big data. 1–2. 2 indexed citations
16.
O’Mahony, Frank, Nicola Da Dalt, Ken Chang, et al.. (2014). F6: Energy-efficient I/O design for next-generation systems. 520–521.
17.
Savoj, Jafar, Parag Upadhyaya, Fu-Tai An, et al.. (2012). Design of high-speed wireline transceivers for backplane communications in 28nm CMOS. 46. 1–4. 21 indexed citations
18.
Chang, Ken, et al.. (2011). Development on ultra high density memory package with PoP structure. 4. 1136–1140. 4 indexed citations
19.
Wu, Ting, Xudong Shi, Kambiz Kaviani, et al.. (2008). Clocking circuits for a 16Gb/s memory interface. 435–438. 14 indexed citations
20.
Chang, Ken, Mats Holmberg, & Oussama Khatib. (2002). The augmented object model: cooperative manipulation and parallel mechanism dynamics. 1. 470–475. 46 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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