Ken Chang

1.5k total citations
60 papers, 1.1k citations indexed

About

Ken Chang is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Ken Chang has authored 60 papers receiving a total of 1.1k indexed citations (citations by other indexed papers that have themselves been cited), including 59 papers in Electrical and Electronic Engineering, 16 papers in Hardware and Architecture and 14 papers in Biomedical Engineering. Recurrent topics in Ken Chang's work include Advancements in PLL and VCO Technologies (47 papers), Radio Frequency Integrated Circuit Design (33 papers) and VLSI and Analog Circuit Testing (15 papers). Ken Chang is often cited by papers focused on Advancements in PLL and VCO Technologies (47 papers), Radio Frequency Integrated Circuit Design (33 papers) and VLSI and Analog Circuit Testing (15 papers). Ken Chang collaborates with scholars based in United States, South Korea and Belgium. Ken Chang's co-authors include Yohan Frans, Parag Upadhyaya, Jay Im, Geoff G. Z. Zhang, Lei Zhou, Hongtao Zhang, Toan Thang Pham, Stanley Chen, Arianne Roldan and Hiva Hedayati and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Advanced Packaging and IEEE Solid-State Circuits Magazine.

In The Last Decade

Ken Chang

56 papers receiving 1.1k citations

Peers

Countries citing papers authored by Ken Chang

Since Specialization

Citations

This map shows the geographic impact of Ken Chang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ken Chang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ken Chang more than expected).

Fields of papers citing papers by Ken Chang

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ken Chang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ken Chang. The network helps show where Ken Chang may publish in the future.

Co-authorship network of co-authors of Ken Chang

This figure shows the co-authorship network connecting the top 25 collaborators of Ken Chang. A scholar is included among the top collaborators of Ken Chang based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ken Chang. Ken Chang is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A 32 Gb/s 0.36 pJ/bit 3 nm Chiplet IO Using 2.5-D CoWoS Package With Real-Time and Per-Lane CDR and Bathtub Monitoring 2025 ·IEEE Journal of Solid-State Circuits ·(unknown), (unknown), (unknown), (unknown), Xin Zhang, (unknown), Hui Wang, Ken Chang	1
2	A 0.52pJ/bit 0.448Tbps/mm UCIe Standard Package Die-to-Die Transceiver with Low-Latency TX Clock Alignment in 3nm FinFET 2025 ·(unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), Ken Chang	0
3	A 32Gb/s 0.36pJ/bit 3nm Chiplet IO Using 2.5D CoWoS Package with Real-Time and Per-Lane CDR and Bathtub Monitoring 2024 ·Juping Gu, Jun Ma, Jun Guo, Fei Guo, Desheng Liang, Yong Li, (unknown), Peng Gao, (unknown), (unknown), (unknown), H. Wang, Can Cui, (unknown), (unknown), Ken Chang	2
4	Design of a 50-Gb/s Hybrid Integrated Si-Photonic Optical Link in 16-nm FinFET 2020 ·IEEE Journal of Solid-State Circuits ·Mayank Raj, Yohan Frans, Ping-Chuan Chiang, (unknown), (unknown), Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, (unknown), (unknown), Ken Chang	40
5	A 7.4-to-14GHz PLL with 54fs<inf>rms</inf> jitter in 16nm FinFET for integrated RF-data-converter SoCs 2018 ·(unknown), (unknown), Parag Upadhyaya, Bob Verbruggen, Ying Cao, (unknown), (unknown), Brendan Farley, Yohan Frans, Ken Chang	53
6	A 4-to-16GHz inverter-based injection-locked quadrature clock generator with phase interpolators for multi-standard I/Os in 7nm FinFET 2018 ·Stanley Chen, Lei Zhou, (unknown), Jay Im, (unknown), (unknown), Mayank Raj, Jaewook Shin, Yohan Frans, Ken Chang	42
7	Design techniques for 32.75Gb/s and 56Gb/s wireline transceivers in 16nm FinFET 2017 ·(unknown), Parag Upadhyaya, Jay Im, Stanley Chen, Yohan Frans, Ken Chang	3
8	A 40-to-56 Gb/s PAM-4 Receiver With Ten-Tap Direct Decision-Feedback Equalization in 16-nm FinFET 2017 ·IEEE Journal of Solid-State Circuits ·Jay Im, (unknown), Arianne Roldan, Ronan Casey, Stanley Chen, (unknown), (unknown), (unknown), (unknown), Lei Zhou, (unknown), Jaeduk Han, Sen Lin, Parag Upadhyaya, (unknown), Yohan Frans, Ken Chang	47
9	A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET 2017 ·IEEE Journal of Solid-State Circuits ·Yohan Frans, Jaewook Shin, Lei Zhou, Parag Upadhyaya, Jay Im, (unknown), (unknown), Hiva Hedayati, Toan Thang Pham, (unknown), (unknown), Geoff G. Z. Zhang, Hongtao Zhang, Ken Chang	127
10	10.6 A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS 2016 ·Ahmed Elkholy, (unknown), (unknown), Ken Chang, Pavan Kumar Hanumolu	21
11	A 0.5-16.3Gbps multi-standard serial transceiver with 219mW/channel in 16nm FinFET 2016 ·(unknown), (unknown), Declan Carey, Ronan Casey, (unknown), (unknown), (unknown), (unknown), (unknown), (unknown), Yohan Frans, Jay Im, Parag Upadhyaya, Wenfeng Zhang, Winson Lin, (unknown), Ken Chang	4
12	A 40-to-64 Gb/s NRZ Transmitter With Supply-Regulated Front-End in 16 nm FinFET 2016 ·IEEE Journal of Solid-State Circuits ·Yohan Frans, (unknown), Hiva Hedayati, (unknown), (unknown), Winson Lin, Jay Im, Parag Upadhyaya, Ken Chang	23
13	F6: Energy-efficient I/O design for next-generation systems 2014 ·Frank O’Mahony, Nicola Da Dalt, Ken Chang, Hisakatsu Yamaguchi, Chulwoo Kim, Elad Alon	0
14	Device aware high-speed transceiver design in planar and FinFet technologies 2014 ·Ken Chang, Jafar Savoj, Parag Upadhyaya, Yohan Frans	1
15	Design of high-speed wireline transceivers for backplane communications in 28nm CMOS 2012 ·Jafar Savoj, (unknown), Parag Upadhyaya, Fu-Tai An, Jay Im, (unknown), (unknown), (unknown), Daniel Wu, Elad Alon, Ken Chang	21
16	A 0.4mW/Gb/s 16Gb/s near-ground receiver front-end with replica transconductance termination calibration 2012 ·Kambiz Kaviani, Amir Amirkhany, (unknown), (unknown), (unknown), Keisuke Saito, (unknown), (unknown), (unknown), Ken Chang, Chuck Yuan	20
17	Development on ultra high density memory package with PoP structure 2011 ·(unknown), (unknown), (unknown), Ken Chang, (unknown)	4
18	Clocking circuits for a 16Gb/s memory interface 2008 ·Ting Wu, Xudong Shi, Kambiz Kaviani, Haechang Lee, Jung‐Hoon Chun, (unknown), Jie Shen, (unknown), Ken Chang	14
19	Design and analysis of a TB/sec memory system 2008 ·W.T. Beyene, (unknown), Nam Hoon Kim, (unknown), (unknown), (unknown), Chuck Yuan, (unknown), Ken Chang	5
20	The augmented object model: cooperative manipulation and parallel mechanism dynamics 2002 ·Ken Chang, Mats Holmberg, Oussama Khatib	46

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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