J. Wei

822 total citations
15 papers, 522 citations indexed

About

J. Wei is a scholar working on Electrical and Electronic Engineering, Biomedical Engineering and Radiology, Nuclear Medicine and Imaging. According to data from OpenAlex, J. Wei has authored 15 papers receiving a total of 522 indexed citations (citations by other indexed papers that have themselves been cited), including 12 papers in Electrical and Electronic Engineering, 3 papers in Biomedical Engineering and 2 papers in Radiology, Nuclear Medicine and Imaging. Recurrent topics in J. Wei's work include Advancements in PLL and VCO Technologies (11 papers), Photonic and Optical Devices (5 papers) and Radio Frequency Integrated Circuit Design (4 papers). J. Wei is often cited by papers focused on Advancements in PLL and VCO Technologies (11 papers), Photonic and Optical Devices (5 papers) and Radio Frequency Integrated Circuit Design (4 papers). J. Wei collaborates with scholars based in United States, China and Taiwan. J. Wei's co-authors include Mark Horowitz, Jared Zerbe, C. Werner, A. Ho, Vladimir Stojanović, Kevin Donnelly, G. Tsang, Ravi Kollipara, E. Alon and B.W. Garlepp and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, Advanced Healthcare Materials and Quantitative Imaging in Medicine and Surgery.

In The Last Decade

J. Wei

12 papers receiving 496 citations

Peers

Countries citing papers authored by J. Wei

Since Specialization

Citations

This map shows the geographic impact of J. Wei's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by J. Wei with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites J. Wei more than expected).

Fields of papers citing papers by J. Wei

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by J. Wei. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by J. Wei. The network helps show where J. Wei may publish in the future.

Co-authorship network of co-authors of J. Wei

This figure shows the co-authorship network connecting the top 25 collaborators of J. Wei. A scholar is included among the top collaborators of J. Wei based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with J. Wei. J. Wei is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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15 of 15 papers shown

#	Work	Indexed citations
1	MHAU-Net: a multi-scale hybrid attention U-shaped network for the segmentation of MRI breast tumors 2025 ·Quantitative Imaging in Medicine and Surgery ·(unknown), (unknown), Xinzhe Luo, Wenxiang Shen, Hai Liao, (unknown), Wei Kang, Min Xu, J. Wei, (unknown), Danke Su	0
2	Minimally Invasive, High Transmittance, Adhesive and Antioxidative Hydrogel Complex for Treatments of Both Optic Neuropathy and Retinopathy 2025 ·Advanced Healthcare Materials ·(unknown), J. Wei, (unknown), (unknown), Yu‐Ting Lin, Ta‐Ching Chen, Jiashing Yu	0
3	A 25 GHz Fast-Lock Digital LC PLL With Multiphase Output Using a Magnetically-Coupled Loop of Oscillators 2014 ·IEEE Journal of Solid-State Circuits ·(unknown), Farshid Aryanfar, J. Wei, (unknown), Reza Navid	34
4	A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface 2014 ·IEEE Journal of Solid-State Circuits ·Masum Hossain, (unknown), (unknown), (unknown), (unknown), J. Wei, (unknown), (unknown), (unknown), J.C. Eble, (unknown), Jared Zerbe	14
5	A 25GHz 100ns lock time digital LC PLL with an 8-phase output clock 2013 ·Reza Navid, (unknown), Farshid Aryanfar, J. Wei, (unknown)	5
6	A 400MHz – 1.6GHz fast lock, jitter filtering ADDLL based burst mode memory interface 2013 ·Masum Hossain, (unknown), (unknown), (unknown), (unknown), J. Wei, (unknown), (unknown), Tran C. Chanh, J.C. Eble, (unknown), Jared Zerbe	4
7	Autonomous Dual-Mode (PAM2/4) Serial Link Transceiver with Adaptive Equalization and Data Recovery 2005 ·Vladimir Stojanović, (unknown), Fred K. Chen, J. Wei, G. Tsang, (unknown), (unknown), Ravi Kollipara, C. Werner, Jared Zerbe, Mark Horowitz	6
8	Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery 2005 ·IEEE Journal of Solid-State Circuits ·Vladimir Stojanović, A. Ho, B.W. Garlepp, (unknown), J. Wei, G. Tsang, E. Alon, Ravi Kollipara, C. Werner, Jared Zerbe, Mark Horowitz	113
9	Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver 2004 ·Vladimir Stojanović, A. Ho, B.W. Garlepp, (unknown), J. Wei, E. Alon, C. Werner, Jared Zerbe, Mark Horowitz	48
10	Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell 2003 ·Jared Zerbe, C. Werner, Vladimir Stojanović, (unknown), J. Wei, G. Tsang, (unknown), William Stonecypher, A. Ho, T.P. Thrush, Ravi Kollipara, (unknown), Mark Horowitz, Kevin Donnelly	27
11	A 0.4-4 Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs 2003 ·(unknown), J. Wei, (unknown), (unknown), Kevin Donnelly, Ching-Chao Huang, S. Sidiropoulos	19
12	Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell 2003 ·IEEE Journal of Solid-State Circuits ·Jared Zerbe, C. Werner, Vladimir Stojanović, (unknown), J. Wei, G. Tsang, (unknown), William Stonecypher, A. Ho, T.P. Thrush, Ravi Kollipara, Mark Horowitz, Kevin Donnelly	161
13	A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs 2003 ·IEEE Journal of Solid-State Circuits ·(unknown), J. Wei, Ching-Chao Huang, (unknown), Kevin Donnelly, Mark Horowitz, Ying Li, S. Sidiropoulos	80
14	A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC 2002 ·Kevin Donnelly, (unknown), (unknown), (unknown), Samir Patel, Brian Lau, Jun Kim, (unknown), Ching-Chao Huang, J. Wei, (unknown), (unknown), M. Johnson	0
15	A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC 1996 ·IEEE Journal of Solid-State Circuits ·Kevin Donnelly, (unknown), (unknown), (unknown), (unknown), (unknown), Jun Kim, (unknown), Ching-Chao Huang, J. Wei, (unknown), (unknown), (unknown), D. Stark, M. Johnson	11

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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