S.K. Goel

595 total citations
17 papers, 466 citations indexed

About

S.K. Goel is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Media Technology. According to data from OpenAlex, S.K. Goel has authored 17 papers receiving a total of 466 indexed citations (citations by other indexed papers that have themselves been cited), including 17 papers in Electrical and Electronic Engineering, 16 papers in Hardware and Architecture and 1 paper in Media Technology. Recurrent topics in S.K. Goel's work include VLSI and Analog Circuit Testing (16 papers), Integrated Circuits and Semiconductor Failure Analysis (14 papers) and VLSI and FPGA Design Techniques (7 papers). S.K. Goel is often cited by papers focused on VLSI and Analog Circuit Testing (16 papers), Integrated Circuits and Semiconductor Failure Analysis (14 papers) and VLSI and FPGA Design Techniques (7 papers). S.K. Goel collaborates with scholars based in Netherlands, Finland and United States. S.K. Goel's co-authors include Bart Vermeulen, Erik Jan Marinissen, Krishnendu Chakrabarty, José Pineda de Gyvez, Maurice Meijer, Anuja Sehgal, Urban Ingelsson, Erik Larsson, Brandon Noia and Jouke Verbree and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IET Computers & Digital Techniques and HAL (Le Centre pour la Communication Scientifique Directe).

In The Last Decade

S.K. Goel

17 papers receiving 442 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
S.K. Goel Netherlands	12	435	420	64	35	7	17	466
Samy Makar United States	10	310 0.7×	343 0.8×	62 1.0×	25 0.7×	12 1.7×	16	380
A.S.M. Hassan Canada	5	309 0.7×	320 0.8×	28 0.4×	40 1.1×	3 0.4×	6	340
Yannick Bonhomme France	10	347 0.8×	379 0.9×	25 0.4×	54 1.5×	6 0.9×	25	396
M.H. Tehranipour United States	8	265 0.6×	268 0.6×	48 0.8×	42 1.2×	24 3.4×	13	302
G. Hetherington United States	6	451 1.0×	447 1.1×	20 0.3×	65 1.9×	4 0.6×	8	466
D.B. Lavo United States	9	306 0.7×	304 0.7×	96 1.5×	64 1.8×	3 0.4×	10	397
Kuo-Liang Cheng Taiwan	11	337 0.8×	339 0.8×	67 1.0×	57 1.6×	10 1.4×	23	388
M. Lousberg Netherlands	11	759 1.7×	743 1.8×	91 1.4×	107 3.1×	5 0.7×	21	804
S. Shoukourian Switzerland	10	289 0.7×	298 0.7×	58 0.9×	23 0.7×	25 3.6×	32	350
Sobeeh Almukhaizim United States	12	280 0.6×	319 0.8×	34 0.5×	14 0.4×	11 1.6×	37	336

Countries citing papers authored by S.K. Goel

Since Specialization

Citations

This map shows the geographic impact of S.K. Goel's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by S.K. Goel with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites S.K. Goel more than expected).

Fields of papers citing papers by S.K. Goel

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by S.K. Goel. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by S.K. Goel. The network helps show where S.K. Goel may publish in the future.

Co-authorship network of co-authors of S.K. Goel

This figure shows the co-authorship network connecting the top 25 collaborators of S.K. Goel. A scholar is included among the top collaborators of S.K. Goel based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with S.K. Goel. S.K. Goel is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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17 of 17 papers shown

Goel, S.K., et al.. (2023). IoT Based Smart Refrigerator and Shopping System Prototype. 1–5. 2 indexed citations

Noia, Brandon, Krishnendu Chakrabarty, S.K. Goel, Erik Jan Marinissen, & Jouke Verbree. (2011). Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 30(11). 1705–1718. 43 indexed citations

Goel, S.K., Maurice Meijer, & José Pineda de Gyvez. (2007). Efficient testing and diagnosis of faulty power switches in SOCs. IET Computers & Digital Techniques. 1(3). 230–236. 8 indexed citations

Sehgal, Anuja, S.K. Goel, Erik Jan Marinissen, & Krishnendu Chakrabarty. (2006). Hierarchy-Aware and Area-Efficient Test Infrastructure Design for Core-Based System Chips. 18. 1–6. 12 indexed citations

Goel, S.K., Maurice Meijer, & José Pineda de Gyvez. (2006). Testing and Diagnosis of Power Switches in SOCs. TU/e Research Portal. 145–150. 27 indexed citations

Goel, S.K. & Erik Jan Marinissen. (2005). On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. Design, Automation, and Test in Europe. 44–49. 14 indexed citations

Ingelsson, Urban, S.K. Goel, Erik Larsson, & Erik Jan Marinissen. (2005). Test Scheduling for Modular SOCs in an Abort-on-Fail Environment. Lund University Publications (Lund University). 8–13. 36 indexed citations

Sehgal, Anuja, S.K. Goel, Erik Jan Marinissen, & Krishnendu Chakrabarty. (2005). IEEE P1500-compliant test wrapper design for hierarchical cores. 1203–1212. 26 indexed citations

Goel, S.K., et al.. (2004). User-constrained test architecture design for modular SOC testing. HAL (Le Centre pour la Communication Scientifique Directe). 80–85. 3 indexed citations

10.

Goel, S.K. & Erik Jan Marinissen. (2004). Control-aware test architecture design for modular SOC testing. 57–62. 33 indexed citations

11.

Goel, S.K. & Erik Jan Marinissen. (2003). A novel test time reduction algorithm for test architecture design for core-based system chips. 7–12. 9 indexed citations

12.

Goel, S.K. & Bart Vermeulen. (2003). Data invalidation analysis for scan-based debug on multiple-clock system chips. 61–66. 2 indexed citations

13.

Iyengar, V., S.K. Goel, Erik Jan Marinissen, & Krishnendu Chakrabarty. (2003). Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints. 1159–1168. 31 indexed citations

14.

Goel, S.K. & Erik Jan Marinissen. (2003). Cluster-based test architecture design for system-on-chip. 259–264. 35 indexed citations

15.

Goel, S.K. & Bart Vermeulen. (2003). Hierarchical data invalidation analysis for scan-based debug on multiple-clock system chips. 21 indexed citations

16.

Vermeulen, Bart, et al.. (2003). Core-based scan architecture for silicon debug. 638–647. 70 indexed citations

17.

Vermeulen, Bart & S.K. Goel. (2002). Design for debug: catching design errors in digital chips. IEEE Design & Test of Computers. 19(3). 35–43. 94 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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