Xiaole Cui

711 total citations
117 papers, 465 citations indexed

About

Xiaole Cui is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Cellular and Molecular Neuroscience. According to data from OpenAlex, Xiaole Cui has authored 117 papers receiving a total of 465 indexed citations (citations by other indexed papers that have themselves been cited), including 98 papers in Electrical and Electronic Engineering, 40 papers in Hardware and Architecture and 19 papers in Cellular and Molecular Neuroscience. Recurrent topics in Xiaole Cui's work include Advanced Memory and Neural Computing (37 papers), Physical Unclonable Functions (PUFs) and Hardware Security (25 papers) and Integrated Circuits and Semiconductor Failure Analysis (23 papers). Xiaole Cui is often cited by papers focused on Advanced Memory and Neural Computing (37 papers), Physical Unclonable Functions (PUFs) and Hardware Security (25 papers) and Integrated Circuits and Semiconductor Failure Analysis (23 papers). Xiaole Cui collaborates with scholars based in China, Hong Kong and United States. Xiaole Cui's co-authors include Xiaoxin Cui, Hao-Miao Zhou, Yufeng Jin, Dunshan Yu, Guangyi Shi, Min Miao, Yufeng Jin, Xinnan Lin, Yuexian Zou and Wen J. Li and has published in prestigious journals such as IEEE Transactions on Industrial Electronics, IEEE Access and IEEE Transactions on Electron Devices.

In The Last Decade

Xiaole Cui

101 papers receiving 448 citations

Author Peers

Peers are selected by citation overlap in the author's most active subfields. citations · hero ref

Author						Papers	Cites
Xiaole Cui	325	102	69	59	50	117	465
Qiming Zou	218 0.7×	46 0.5×	123 1.8×	31 0.5×	22 0.4×	27	431
M. Pasotti	532 1.6×	59 0.6×	92 1.3×	66 1.1×	36 0.7×	51	617
Peter Debacker	817 2.5×	152 1.5×	63 0.9×	88 1.5×	25 0.5×	73	924
Kai–Chiang Wu	467 1.4×	144 1.4×	38 0.6×	34 0.6×	23 0.5×	70	667
Vineet Sahula	269 0.8×	67 0.7×	94 1.4×	119 2.0×	15 0.3×	68	554
Emre Salman	689 2.1×	229 2.2×	36 0.5×	78 1.3×	38 0.8×	99	852
Alexandre Valentian	622 1.9×	127 1.2×	30 0.4×	72 1.2×	62 1.2×	59	708
Naoya Watanabe	633 1.9×	135 1.3×	53 0.8×	38 0.6×	26 0.5×	132	800
Jie Lin	294 0.9×	27 0.3×	96 1.4×	59 1.0×	42 0.8×	42	472
Ebrahim Abiri	803 2.5×	34 0.3×	29 0.4×	46 0.8×	46 0.9×	132	939

Countries citing papers authored by Xiaole Cui

Since Specialization

Citations

This map shows the geographic impact of Xiaole Cui's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Xiaole Cui with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Xiaole Cui more than expected).

Fields of papers citing papers by Xiaole Cui

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Xiaole Cui. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Xiaole Cui. The network helps show where Xiaole Cui may publish in the future.

Co-authorship network of co-authors of Xiaole Cui

This figure shows the co-authorship network connecting the top 25 collaborators of Xiaole Cui. A scholar is included among the top collaborators of Xiaole Cui based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Xiaole Cui. Xiaole Cui is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

Cui, Xiaole, et al.. (2025). A VC Dimension-Oriented Improvement Method of PUFs for the Anti-Modeling-Attack Capability. ACM Transactions on Embedded Computing Systems. 24(5). 1–30.

Cui, Xiaole, et al.. (2025). A Reconfigurable Built-In Self-Test Scheme for the Evaluation Circuits of Digital SRAM-IMC Architectures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 34(1). 280–293.

Cui, Xiaole, et al.. (2024). Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique. IEEE Transactions on Device and Materials Reliability. 24(3). 390–400. 1 indexed citations

Cui, Xiaole, et al.. (2024). The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice. Microelectronics Journal. 144. 106088–106088. 1 indexed citations

Cui, Xiaole, Xiaole Cui, Wei Feng, et al.. (2024). A reconfigurable FPGA-based spiking neural network accelerator. Microelectronics Journal. 152. 106377–106377. 1 indexed citations

Cui, Xiaole, et al.. (2024). A Network-Coding-Based Functional Test Method for Routers in 3-D Mesh NoCs. IEEE Internet of Things Journal. 12(8). 9940–9953.

Li, Lun, Jiawei Wang, Hanqing Liu, et al.. (2024). SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow. 1–5. 2 indexed citations

Cui, Xiaole, et al.. (2024). A Convolutional Spiking Neural Network Accelerator with the Sparsity-Aware Memory and Compressed Weights. 28. 163–171. 2 indexed citations

Zeng, Yang & Xiaole Cui. (2024). A High Performance PODEM Algorithm with the Improved Backtrace Process. 1–6. 1 indexed citations

10.

Cui, Xiaole, et al.. (2023). An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs. IEEE Transactions on Information Forensics and Security. 18. 1773–1788. 6 indexed citations

11.

Huang, Huixian, et al.. (2022). An obfuscation scheme of scan chain to protect the cryptographic chips. 19–24. 2 indexed citations

12.

Cui, Xiaole, et al.. (2022). The Design Method of Logic Circuits based on the Voltage-Input Enhanced Scouting Logic Gates. 136–142.

13.

Chen, Wei, et al.. (2021). Repair the faulty TSVs with the improved FNS-CAC codec. 28(2). 1. 2 indexed citations

14.

Cui, Xiaole, et al.. (2020). The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates. IEEE Access. 9. 54466–54477. 8 indexed citations

15.

Li, Xianfeng, et al.. (2020). ReTriple: Reduction of Redundant Rendering on Android Devices for Performance and Energy Optimizations. 1–6. 6 indexed citations

16.

Zhou, Hang, Po‐Hsun Chen, Chih‐Cheng Shih, et al.. (2018). Enhancing the Electrical Uniformity and Reliability of the HfO₂-Based RRAM Using High-Permittivity Ta₂O₅ Side Wall. IEEE Journal of the Electron Devices Society. 6. 627–632. 17 indexed citations

17.

Cui, Xiaole, et al.. (2017). A time-delay based RRAM PUF circuit. 1–2. 1 indexed citations

18.

Cui, Xiaole, et al.. (2016). An algorithm of training sample selection for integrated circuit device modeling based on artificial neural networks. Rare & Special e-Zone (The Hong Kong University of Science and Technology). 314–317. 2 indexed citations

19.

Zhang, Xinxing, et al.. (2014). Critical parasitic capacitance in nano-scale phase-change memory (PCM) cell. Rare & Special e-Zone (The Hong Kong University of Science and Technology). 1–2. 1 indexed citations

20.

Cui, Xiaole, et al.. (2012). Modeling and testing of interference faults in the nano NAND flash memory. Design, Automation, and Test in Europe. 527–531. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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