Xiaoxin Cui

917 total citations
134 papers, 577 citations indexed

About

Xiaoxin Cui is a scholar working on Electrical and Electronic Engineering, Artificial Intelligence and Hardware and Architecture. According to data from OpenAlex, Xiaoxin Cui has authored 134 papers receiving a total of 577 indexed citations (citations by other indexed papers that have themselves been cited), including 109 papers in Electrical and Electronic Engineering, 37 papers in Artificial Intelligence and 29 papers in Hardware and Architecture. Recurrent topics in Xiaoxin Cui's work include Advanced Memory and Neural Computing (73 papers), Ferroelectric and Negative Capacitance Devices (46 papers) and Physical Unclonable Functions (PUFs) and Hardware Security (22 papers). Xiaoxin Cui is often cited by papers focused on Advanced Memory and Neural Computing (73 papers), Ferroelectric and Negative Capacitance Devices (46 papers) and Physical Unclonable Functions (PUFs) and Hardware Security (22 papers). Xiaoxin Cui collaborates with scholars based in China, United States and Singapore. Xiaoxin Cui's co-authors include Xiaole Cui, Dunshan Yu, Yuan Wang, Kefei Liu, Ru Huang, Kai Liao, Xin’an Wang, Yi Zhong, Kaisheng Ma and Zhenhui Dai and has published in prestigious journals such as SHILAP Revista de lepidopterología, IEEE Transactions on Industrial Electronics and IEEE Access.

In The Last Decade

Xiaoxin Cui

118 papers receiving 561 citations

Peers

Countries citing papers authored by Xiaoxin Cui

Since Specialization

Citations

This map shows the geographic impact of Xiaoxin Cui's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Xiaoxin Cui with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Xiaoxin Cui more than expected).

Fields of papers citing papers by Xiaoxin Cui

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Xiaoxin Cui. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Xiaoxin Cui. The network helps show where Xiaoxin Cui may publish in the future.

Co-authorship network of co-authors of Xiaoxin Cui

This figure shows the co-authorship network connecting the top 25 collaborators of Xiaoxin Cui. A scholar is included among the top collaborators of Xiaoxin Cui based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Xiaoxin Cui. Xiaoxin Cui is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	A VC Dimension-Oriented Improvement Method of PUFs for the Anti-Modeling-Attack Capability 2025 ·ACM Transactions on Embedded Computing Systems ·(unknown), Xiaole Cui, (unknown), Xiaoxin Cui	0
2	Towards Effective and Sparse Adversarial Attack on Spiking Neural Networks via Breaking Invisible Surrogate Gradients 2025 ·Lun Li, (unknown), Qin Ni, Ling Liang, Yuan Wang, (unknown), Dunshan Yu, Xiaoxin Cui	0
3	A 16.41 TOPS/W CNN Accelerator with Event-Based Layer Fusion for Real-Time Inference 2024 ·J. Wang, Lun Li, Zhenhui Dai, (unknown), Xiaoxin Cui	1
4	NeuroREC: A 28-nm Efficient Neuromorphic Processor for Radar Emitter Classification 2024 ·IEEE Transactions on Circuits and Systems I Regular Papers ·(unknown), (unknown), (unknown), (unknown), Lun Li, (unknown), Jian Cao, Xiaoxin Cui, (unknown), Yuan Wang	0
5	A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array 2024 ·Zilin Wang, (unknown), Guang Chen, Shuo Feng, (unknown), Xiaoxin Cui, Yuan Wang	1
6	Design of Highly Reliable 14T and 16T SRAM Cells Combined With Layout Harden Technique 2024 ·IEEE Transactions on Device and Materials Reliability ·(unknown), Xiaole Cui, (unknown), (unknown), Xiaoxin Cui, Xing Zhang	1
7	The area-efficient gate level information flow tracking schemes of digital circuit with multi-level security lattice 2024 ·Microelectronics Journal ·(unknown), Xiaole Cui, (unknown), Xiaoxin Cui, Xing Zhang	1
8	An all integer-based spiking neural network with dynamic threshold adaptation 2024 ·Frontiers in Neuroscience ·(unknown), Xiaoxin Cui, Shuo Feng, (unknown), Yi Zhong, Zhenhui Dai, Yuan Wang	2
9	An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow 2024 ·Zhenhui Dai, Jiawei Wang, Yi Zhong, (unknown), Cheng Zhao, (unknown), (unknown), Yuan Wang, Dunshan Yu, Xiaoxin Cui	1
10	SPAT: FPGA-based Sparsity-Optimized Spiking Neural Network Training Accelerator with Temporal Parallel Dataflow 2024 ·(unknown), Lun Li, Jiawei Wang, (unknown), Hanqing Liu, Zhenhui Dai, Xiaole Cui, Xiaoxin Cui	2
11	A reconfigurable FPGA-based spiking neural network accelerator 2024 ·Microelectronics Journal ·(unknown), Xiaole Cui, Wei Feng, Hanqing Liu, (unknown), Xiaoxin Cui	1
12	An Evaluation Method of the Anti-Modeling-Attack Capability of PUFs 2023 ·IEEE Transactions on Information Forensics and Security ·(unknown), Xiaole Cui, (unknown), Xiaoxin Cui	6
13	Toward a Lossless Conversion for Spiking Neural Networks with Negative‐Spike Dynamics 2023 ·SHILAP Revista de lepidopterología ·(unknown), Xiaoxin Cui, Guang Chen, (unknown), Yuan Wang	1
14	An obfuscation scheme of scan chain to protect the cryptographic chips 2022 ·Huixian Huang, Xiaole Cui, (unknown), Ge Li, Xiaoxin Cui	2
15	A 4-bit Integer-Only Neural Network Quantization Method Based on Shift Batch Normalization 2022 ·2022 IEEE International Symposium on Circuits and Systems (ISCAS) ·Qingyu Guo, Xiaoxin Cui, Jian Zhang, (unknown), Xinjie Guo, Yuan Wang	3
16	A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS 2021 ·IEEE Transactions on Circuits & Systems II Express Briefs ·(unknown), Xiaoxin Cui, Yi Zhong, Kefei Liu, (unknown), Zhenhui Dai, Yuan Wang, Dunshan Yu, Ru Huang	43
17	A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS 2021 ·Yi Zhong, Xiaoxin Cui, (unknown), Kefei Liu, Yuan Wang, Ru Huang	12
18	A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations 2021 ·(unknown), Xiaoxin Cui, Yi Zhong, Kefei Liu, (unknown), Zhenhui Dai, Dunshan Yu, Yuan Wang, Ru Huang	6
19	The Synthesis Method of Logic Circuits Based on the NMOS-Like RRAM Gates 2020 ·IEEE Access ·Xiaole Cui, Ye Ma, (unknown), Xiaoxin Cui	8
20	A Hardware Implementation of SNN-Based Spatio-Temporal Memory Model 2019 ·Frontiers in Neuroscience ·Kefei Liu, Xiaoxin Cui, Yi Zhong, (unknown), Yuan Wang, Huajin Tang, Ru Huang	13

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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