H.T. Vierhaus

937 total citations
109 papers, 595 citations indexed

About

H.T. Vierhaus is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, H.T. Vierhaus has authored 109 papers receiving a total of 595 indexed citations (citations by other indexed papers that have themselves been cited), including 98 papers in Hardware and Architecture, 98 papers in Electrical and Electronic Engineering and 10 papers in Computer Networks and Communications. Recurrent topics in H.T. Vierhaus's work include VLSI and Analog Circuit Testing (86 papers), Radiation Effects in Electronics (68 papers) and Integrated Circuits and Semiconductor Failure Analysis (60 papers). H.T. Vierhaus is often cited by papers focused on VLSI and Analog Circuit Testing (86 papers), Radiation Effects in Electronics (68 papers) and Integrated Circuits and Semiconductor Failure Analysis (60 papers). H.T. Vierhaus collaborates with scholars based in Germany, United States and Italy. H.T. Vierhaus's co-authors include U. Gläser, Christian Jacobi, Uwe Hübner, Sebastian Müller, P. Prinetto, M. Sonza Reorda, Raimund Ubar, Fulvio Corno, Mario Porrmann and Hans G. Kerkhoff and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Solid-State Electronics and IEEE Micro.

In The Last Decade

H.T. Vierhaus

94 papers receiving 550 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
H.T. Vierhaus Germany 13 524 512 64 48 40 109 595
Srivaths Ravi United States 11 296 0.6× 334 0.7× 75 1.2× 40 0.8× 37 0.9× 43 419
Rohit Kapur United States 13 462 0.9× 494 1.0× 26 0.4× 31 0.6× 86 2.1× 46 537
Michael A. Kochte Germany 17 748 1.4× 788 1.5× 90 1.4× 45 0.9× 41 1.0× 76 871
S. Venkataraman United States 12 690 1.3× 702 1.4× 22 0.3× 45 0.9× 107 2.7× 27 745
Riccardo Cantoro Italy 11 436 0.8× 452 0.9× 35 0.5× 109 2.3× 50 1.3× 83 525
A. Krstić United States 19 877 1.7× 869 1.7× 31 0.5× 58 1.2× 58 1.4× 32 945
Artur Jutman Estonia 12 372 0.7× 401 0.8× 49 0.8× 24 0.5× 77 1.9× 81 462
J.-Carlos Baraza-Calvo Spain 12 382 0.7× 314 0.6× 56 0.9× 63 1.3× 39 1.0× 31 436
Mahesh A. Iyer United States 13 442 0.8× 447 0.9× 32 0.5× 28 0.6× 15 0.4× 34 507
Dimitri Kagaris United States 11 311 0.6× 307 0.6× 41 0.6× 31 0.6× 55 1.4× 77 393

Countries citing papers authored by H.T. Vierhaus

Since Specialization
Citations

This map shows the geographic impact of H.T. Vierhaus's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by H.T. Vierhaus with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites H.T. Vierhaus more than expected).

Fields of papers citing papers by H.T. Vierhaus

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by H.T. Vierhaus. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by H.T. Vierhaus. The network helps show where H.T. Vierhaus may publish in the future.

Co-authorship network of co-authors of H.T. Vierhaus

This figure shows the co-authorship network connecting the top 25 collaborators of H.T. Vierhaus. A scholar is included among the top collaborators of H.T. Vierhaus based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with H.T. Vierhaus. H.T. Vierhaus is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
2.
Vierhaus, H.T., et al.. (2017). Fault detection and self repair in Hsiao-code FEC circuits. 42–47. 1 indexed citations
3.
Müller, Sebastian, et al.. (2015). A multi-layer software-based fault-tolerance approach for heterogenous multi-core systems. 1–6. 1 indexed citations
4.
Vierhaus, H.T., et al.. (2014). Vergleich der Beschreibung und Simulation einer Befehlssatzarchitektur in LISA und CoMet.. 101–111. 1 indexed citations
5.
Vierhaus, H.T., et al.. (2013). Ein konfigurierbarer Zwischencodesimulator zum compilerzentrierten Mikroprozessorentwurf.. 13–24. 1 indexed citations
6.
Vierhaus, H.T., et al.. (2013). On performance estimation of a scalable VLIW soft-core on ALTERA and XILINX FPGA platforms. International Conference on Applied Electronics. 1–4. 5 indexed citations
7.
Vierhaus, H.T., et al.. (2010). Effective logic self repair based on extracted logic clusters. 1–6. 5 indexed citations
8.
Vierhaus, H.T., et al.. (2009). A comprehensive scheme for logic self repair. 13–18. 2 indexed citations
9.
Vierhaus, H.T., et al.. (2009). A Concept for Logic Self Repair. 621–624. 13 indexed citations
10.
Vierhaus, H.T., et al.. (2007). Fault Injection Techniques and their Accelerated Simulation in SystemC. 587–595. 17 indexed citations
11.
Vierhaus, H.T., et al.. (2006). Built-in Self Repair by Reconfiguration of FPGAs. 187–188. 12 indexed citations
12.
Vierhaus, H.T., et al.. (2004). A hierarchical self test scheme for SoCs. 37–42. 7 indexed citations
13.
Vierhaus, H.T., et al.. (2002). Switch-level fault simulation for non-trivial faults based on abstract data types. 233–237. 4 indexed citations
14.
Vierhaus, H.T., et al.. (2002). CMOS bridges and resistive transistor faults: IDDQ versus delay effects. Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft). 83–91. 47 indexed citations
15.
Gläser, U. & H.T. Vierhaus. (1996). Mixed level test generation for synchronous sequential circuits using the FOGBUSTER algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 15(4). 410–423. 5 indexed citations
16.
Langevin, M., et al.. (1995). A codesign methodology for high performance embedded systems. Publikationsdatenbank der Fraunhofer-Gesellschaft (Fraunhofer-Gesellschaft). 3 indexed citations
17.
Gläser, U., et al.. (1995). Gate delay fault test generation for non-scan circuits. 308–312. 5 indexed citations
18.
Glässer, Uwe & H.T. Vierhaus. (1995). FOGBUSTER: an efficient algorithm for sequential test generation. European Design Automation Conference. 230–235. 2 indexed citations
19.
Gläser, U., et al.. (1994). Test generation for bridging faults in CMOS ICs based on current monitoring versus signal propagation. International Conference on Computer Aided Design. 36–39. 5 indexed citations
20.
Hübner, Uwe & H.T. Vierhaus. (1992). Efficient partitioning and analysis of digital CMOS-circuits. International Conference on Computer Aided Design. 280–283. 2 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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