K. Heragu

511 total citations
16 papers, 373 citations indexed

About

K. Heragu is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Networks and Communications. According to data from OpenAlex, K. Heragu has authored 16 papers receiving a total of 373 indexed citations (citations by other indexed papers that have themselves been cited), including 16 papers in Electrical and Electronic Engineering, 13 papers in Hardware and Architecture and 1 paper in Computer Networks and Communications. Recurrent topics in K. Heragu's work include VLSI and Analog Circuit Testing (13 papers), Integrated Circuits and Semiconductor Failure Analysis (11 papers) and Radiation Effects in Electronics (6 papers). K. Heragu is often cited by papers focused on VLSI and Analog Circuit Testing (13 papers), Integrated Circuits and Semiconductor Failure Analysis (11 papers) and Radiation Effects in Electronics (6 papers). K. Heragu collaborates with scholars based in United States and Germany. K. Heragu's co-authors include Vishwani D. Agrawal, J.H. Patel, M.L. Bushnell, Robert Payne, Song Wu, Vikas Gupta, S. Ramaswamy, P. Landman, Wai Lee and Runqi Gu and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and International Conference on Computer Aided Design.

In The Last Decade

K. Heragu

16 papers receiving 359 citations

Peers

K. Heragu

EEE

HA

BE

CNC

CTM

P. Pant United States

Lerong Cheng United States

S. Bobba United States

Y. Aimoto Japan

Kunhyuk Kang United States

Tuyet Nguyen United States

F. Minami Japan

H.S. Deogun United States

Behnam Amelifard United States

P. Pant United States

K. Heragu

418 ×1.2

EEE

253 ×1.1

HA

27 ×0.7

BE

21 ×1.0

CNC

11 ×0.9

CTM

Citations per year, relative to K. Heragu K. Heragu (= 1×) peers P. Pant

Countries citing papers authored by K. Heragu

Since Specialization

Citations

This map shows the geographic impact of K. Heragu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by K. Heragu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites K. Heragu more than expected).

Fields of papers citing papers by K. Heragu

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by K. Heragu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by K. Heragu. The network helps show where K. Heragu may publish in the future.

Co-authorship network of co-authors of K. Heragu

This figure shows the co-authorship network connecting the top 25 collaborators of K. Heragu. A scholar is included among the top collaborators of K. Heragu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with K. Heragu. K. Heragu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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16 of 16 papers shown

1.

Gammie, Gordon, Alice Wang, Minh Quang Chau, et al.. (2008). A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. 258–611. 58 indexed citations

2.

Payne, Robert, S. Ramaswamy, Song Wu, et al.. (2005). A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications. 68–70. 32 indexed citations

3.

Landman, P., Vikas Gupta, Song Wu, et al.. (2005). A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communications. 66–68. 8 indexed citations

4.

Payne, Robert, P. Landman, S. Ramaswamy, et al.. (2005). A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels. IEEE Journal of Solid-State Circuits. 40(12). 2646–2657. 79 indexed citations

5.

Heragu, K., et al.. (2002). Testing of dynamic logic circuits based on charge sharing. 396–403. 3 indexed citations

6.

Heragu, K., Vishwani D. Agrawal, & M.L. Bushnell. (2002). Statistical methods for delay fault coverage analysis. 166–170. 7 indexed citations

7.

Heragu, K., Vishwani D. Agrawal, & M.L. Bushnell. (2002). FACTS: fault coverage estimation by test vector sampling. 266–271. 8 indexed citations

8.

Heragu, K., et al.. (2002). Test vector generation for charge sharing failures in dynamic logic. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 21(12). 1502–1508. 2 indexed citations

9.

Heragu, K., J.H. Patel, & Vishwani D. Agrawal. (2002). Improving accuracy in path delay fault coverage estimation. 422–425. 7 indexed citations

10.

Heragu, K., J.H. Patel, & Vishwani D. Agrawal. (2002). Segment delay faults: a new fault model. 32–39. 72 indexed citations

11.

Heragu, K., J.H. Patel, & Vishwani D. Agrawal. (1999). A test generator for segment delay faults. 484–491. 4 indexed citations

12.

Heragu, K., J.H. Patel, & Vishwani D. Agrawal. (1997). Fast identification of untestable delay faults using implications. International Conference on Computer Aided Design. 642–647. 46 indexed citations

13.

Heragu, K., Vishwani D. Agrawal, M.L. Bushnell, & J.H. Patel. (1997). Improving a nonenumerative method to estimate path delay fault coverage. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 16(7). 759–762. 13 indexed citations

14.

Heragu, K., J.H. Patel, & Vishwani D. Agrawal. (1996). SIGMA: a simulator for segment delay faults. International Conference on Computer Aided Design. 502–508. 8 indexed citations

15.

Heragu, K., Vishwani D. Agrawal, & M.L. Bushnell. (1995). Fault coverage estimation by test vector sampling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 14(5). 590–596. 6 indexed citations

16.

Heragu, K., M.L. Bushnell, & Vishwani D. Agrawal. (1994). An efficient path delay fault coverage estimator. 516–521. 20 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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