P. Pant

652 total citations
24 papers, 449 citations indexed

About

P. Pant is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Control and Systems Engineering. According to data from OpenAlex, P. Pant has authored 24 papers receiving a total of 449 indexed citations (citations by other indexed papers that have themselves been cited), including 22 papers in Electrical and Electronic Engineering, 13 papers in Hardware and Architecture and 1 paper in Control and Systems Engineering. Recurrent topics in P. Pant's work include VLSI and Analog Circuit Testing (13 papers), Integrated Circuits and Semiconductor Failure Analysis (10 papers) and Low-power high-performance VLSI design (9 papers). P. Pant is often cited by papers focused on VLSI and Analog Circuit Testing (13 papers), Integrated Circuits and Semiconductor Failure Analysis (10 papers) and Low-power high-performance VLSI design (9 papers). P. Pant collaborates with scholars based in United States, India and United Kingdom. P. Pant's co-authors include Mondira Pant, Abhijit Chatterjee, D.S. Wills, Vivek De, Vivek Tiwari, Sandeep K. Gupta, Jim Ignowski, D. Josephson, Janusz Rajski and Geir Egil Eide and has published in prestigious journals such as Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

P. Pant

24 papers receiving 415 citations

Peers

Countries citing papers authored by P. Pant

Since Specialization

Citations

This map shows the geographic impact of P. Pant's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by P. Pant with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites P. Pant more than expected).

Fields of papers citing papers by P. Pant

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by P. Pant. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by P. Pant. The network helps show where P. Pant may publish in the future.

Co-authorship network of co-authors of P. Pant

This figure shows the co-authorship network connecting the top 25 collaborators of P. Pant. A scholar is included among the top collaborators of P. Pant based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with P. Pant. P. Pant is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	The FRENA accelerator and its beam energy calibration 2024 ·Nuclear Instruments and Methods in Physics Research Section A Accelerators Spectrometers Detectors and Associated Equipment ·(unknown), K. Banerjee, (unknown), Pratap Roy, P. Pant, (unknown), G. Mukherjee, Tushar K. Ghosh	1
2	Characterization of EJ-276D plastic scintillator and its comparison with EJ-299-33A and BC-501A 2024 ·Journal of Instrumentation ·P. Pant, K. Banerjee, Pratap Roy, (unknown), A. Saha	3
3	Analog/Digital Data Transmission using Li-Fi 2020 ·(unknown), (unknown), (unknown), P. Pant, (unknown), Vinay Kumar Jadoun	2
4	Streaming Scan Network (SSN): An Efficient Packetized Data Network for Testing of Complex SoCs 2020 ·(unknown), Mark Kassab, (unknown), (unknown), (unknown), (unknown), (unknown), Geir Egil Eide, Janusz Rajski, (unknown), (unknown), (unknown), P. Pant	22
5	Innovative practices session 10C: Delay test 2013 ·P. Pant, (unknown), (unknown), (unknown)	1
6	Hardware hooks for transition scan characterization 2011 ·P. Pant, (unknown)	5
7	Lessons from at-speed scan deployment on an Intel® Itanium® microprocessor 2010 ·P. Pant, (unknown), (unknown), (unknown), (unknown)	13
8	Device-circuit Optimization For Minimal Energy And Power Consumption In Cmos Random Logic Networks 2005 ·P. Pant, Vivek De, Abhijit Chatterjee	1
9	Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits 2003 ·P. Pant, (unknown), Abhijit Chatterjee	7
10	Efficient diagnosis of path delay faults in digital logic circuits 2003 ·P. Pant, Abhijit Chatterjee	4
11	Path-delay fault diagnosis in non-scan sequential circuits with at-speed test application 2002 ·P. Pant, Abhijit Chatterjee	12
12	On-chip decoupling capacitor optimization using architectural level current signature prediction 2002 ·Mondira Pant, P. Pant, D.S. Wills	16
13	Inductive noise reduction at the architectural level 2002 ·Mondira Pant, P. Pant, D.S. Wills, Vivek Tiwari	18
14	Non-robust tests for stuck-fault detection using signal waveform analysis: feasibility and advantages 2002 ·Abhijit Chatterjee, (unknown), P. Pant, Jacob A. Abraham	5
15	On-chip decoupling capacitor optimization using architectural level prediction 2002 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Mondira Pant, P. Pant, D.S. Wills	61
16	Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits 2001 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·P. Pant, (unknown), (unknown)	74
17	Path delay fault diagnosis in combinational circuits with implicit fault enumeration 2001 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·P. Pant, (unknown), Sandeep K. Gupta, Abhijit Chatterjee	20
18	Efficient diagnosis of path delay faults in digital logic circuits 1999 ·International Conference on Computer Aided Design ·P. Pant, Abhijit Chatterjee	10
19	Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits 1998 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·P. Pant, Vivek De, Abhijit Chatterjee	32
20	Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks 1997 ·P. Pant, Vivek De, Abhijit Chatterjee	14

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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