F. Minami

643 total citations
16 papers, 406 citations indexed

About

F. Minami is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computer Vision and Pattern Recognition. According to data from OpenAlex, F. Minami has authored 16 papers receiving a total of 406 indexed citations (citations by other indexed papers that have themselves been cited), including 15 papers in Electrical and Electronic Engineering, 11 papers in Hardware and Architecture and 1 paper in Computer Vision and Pattern Recognition. Recurrent topics in F. Minami's work include Low-power high-performance VLSI design (13 papers), VLSI and FPGA Design Techniques (11 papers) and VLSI and Analog Circuit Testing (7 papers). F. Minami is often cited by papers focused on Low-power high-performance VLSI design (13 papers), VLSI and FPGA Design Techniques (11 papers) and VLSI and Analog Circuit Testing (7 papers). F. Minami collaborates with scholars based in Japan and South Korea. F. Minami's co-authors include Kimiyoshi Usami, M. Igarashi, M. Ichida, Takashi Ishikawa, K. Nogami, M. Kanazawa, Takahiro Aoki, Masanori Hashimoto, Takeshi Kitahara and Masao Yamada and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEICE Transactions on Information and Systems and IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

In The Last Decade

F. Minami

14 papers receiving 370 citations

Peers

F. Minami
M. Ichida Japan
Y. Aimoto Japan
G. Gerosa United States
Tuyet Nguyen United States
K. Nogami Japan
H. Mair United States
C. Dietz United States
Uming Ko United States
H. Partovi United States
Gary Yeap United States
M. Ichida Japan
F. Minami
Citations per year, relative to F. Minami F. Minami (= 1×) peers M. Ichida

Countries citing papers authored by F. Minami

Since Specialization
Citations

This map shows the geographic impact of F. Minami's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by F. Minami with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites F. Minami more than expected).

Fields of papers citing papers by F. Minami

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by F. Minami. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by F. Minami. The network helps show where F. Minami may publish in the future.

Co-authorship network of co-authors of F. Minami

This figure shows the co-authorship network connecting the top 25 collaborators of F. Minami. A scholar is included among the top collaborators of F. Minami based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with F. Minami. F. Minami is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

16 of 16 papers shown
1.
Minami, F., et al.. (2010). Gate Delay Estimation in STA under Dynamic Power Supply Noise. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. E93-A(12). 2447–2455. 16 indexed citations
2.
Minami, F., et al.. (2010). Gate delay estimation in STA under dynamic power supply noise. 775–780. 14 indexed citations
5.
Minami, F., et al.. (2005). Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. Design, Automation, and Test in Europe. 646–647. 8 indexed citations
6.
Minami, F., et al.. (2004). Full-chip analysis method of ESD protection network. 439–444. 8 indexed citations
7.
Minami, F., Masaru Sakurai, & Yuichi Ninomiya. (2003). MUSE decoder. 192–193. 1 indexed citations
8.
Igarashi, M., et al.. (2002). A low-power design method using multiple supply voltages. 1 indexed citations
9.
Usami, Kimiyoshi, K. Nogami, M. Igarashi, et al.. (2002). Automated low-power technique exploiting multiple supply voltages applied to a media processor. 131–134. 37 indexed citations
10.
Kitahara, Takeshi, et al.. (2002). A clock-gating method for low-power LSI design. e79 d. 307–312. 18 indexed citations
11.
Usami, Kimiyoshi, M. Igarashi, F. Minami, et al.. (1998). Automated low-power technique exploiting multiple supply voltages applied to a media processor. IEEE Journal of Solid-State Circuits. 33(3). 463–472. 178 indexed citations
12.
Igarashi, M., M. Kanazawa, M. Ichida, et al.. (1997). A low-power design method using multiple supply voltages. 36–41. 60 indexed citations
13.
Minami, F., et al.. (1996). Delay and Skew Minimized Clock Tree Synthesis for Embedded Arrays (Special Issue on Synthesis and Verification of Hardware Design). IEICE Transactions on Information and Systems. 79(10). 1405–1409. 1 indexed citations
14.
Minami, F., et al.. (1996). Switching activity analysis for sequential circuits using Boolean approximation method. 79–84. 5 indexed citations
15.
Minami, F., et al.. (1995). Switching activity analysis using Boolean approximation method. International Conference on Computer Aided Design. 20–25. 37 indexed citations
16.
Minami, F., et al.. (1992). Clock Tree Synthesis Based On Rc Delay Balancing. 28.3.1–28.3.4. 19 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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