P. Landman

1.3k total citations
18 papers, 854 citations indexed

About

P. Landman is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, P. Landman has authored 18 papers receiving a total of 854 indexed citations (citations by other indexed papers that have themselves been cited), including 18 papers in Electrical and Electronic Engineering, 8 papers in Hardware and Architecture and 3 papers in Biomedical Engineering. Recurrent topics in P. Landman's work include Low-power high-performance VLSI design (11 papers), Embedded Systems Design Techniques (8 papers) and Advancements in PLL and VCO Technologies (8 papers). P. Landman is often cited by papers focused on Low-power high-performance VLSI design (11 papers), Embedded Systems Design Techniques (8 papers) and Advancements in PLL and VCO Technologies (8 papers). P. Landman collaborates with scholars based in United States. P. Landman's co-authors include Jan M. Rabaey, S. Ramaswamy, K. Heragu, Vikas Gupta, Robert Payne, Song Wu, Wai Lee, Runqi Gu, R. Mehra and Hiroshi Takahashi and has published in prestigious journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

P. Landman

18 papers receiving 778 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
P. Landman United States	14	698	527	143	136	91	18	854
Fumihiko Sano Japan	8	629 0.9×	183 0.3×	76 0.5×	195 1.4×	70 0.8×	12	721
K. Sasaki Japan	14	856 1.2×	367 0.7×	100 0.7×	269 2.0×	37 0.4×	34	953
T. Furuyama Japan	14	576 0.8×	213 0.4×	112 0.8×	151 1.1×	134 1.5×	44	731
A. Chiba Japan	9	465 0.7×	142 0.3×	64 0.4×	203 1.5×	65 0.7×	11	532
William J. Bowhill United States	7	800 1.1×	426 0.8×	169 1.2×	109 0.8×	16 0.2×	12	923
R. Mehra United States	6	329 0.5×	318 0.6×	109 0.8×	41 0.3×	47 0.5×	10	456
Ing-Chao Lin Taiwan	12	432 0.6×	222 0.4×	99 0.7×	101 0.7×	22 0.2×	49	537
J. Eno United States	7	638 0.9×	503 1.0×	261 1.8×	179 1.3×	13 0.1×	9	847
Shen-Iuan Liu Taiwan	12	639 0.9×	143 0.3×	40 0.3×	273 2.0×	43 0.5×	25	683
V. Gutnik United States	7	414 0.6×	229 0.4×	127 0.9×	163 1.2×	45 0.5×	7	540

Countries citing papers authored by P. Landman

Since Specialization

Citations

This map shows the geographic impact of P. Landman's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by P. Landman with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites P. Landman more than expected).

Fields of papers citing papers by P. Landman

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by P. Landman. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by P. Landman. The network helps show where P. Landman may publish in the future.

Co-authorship network of co-authors of P. Landman

This figure shows the co-authorship network connecting the top 25 collaborators of P. Landman. A scholar is included among the top collaborators of P. Landman based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with P. Landman. P. Landman is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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18 of 18 papers shown

El-Chammas, Manar, et al.. (2015). 15.8 90dB-SFDR 14b 500MS/S BiCMOS switched-current pipelined ADC. 1–3. 18 indexed citations

Payne, Robert, S. Ramaswamy, Song Wu, et al.. (2005). A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications. 68–70. 32 indexed citations

Landman, P., Vikas Gupta, Song Wu, et al.. (2005). A transmit architecture with 4-tap feedforward equalization for 6.25/12.5Gb/s serial backplane communications. 66–68. 8 indexed citations

Payne, Robert, P. Landman, S. Ramaswamy, et al.. (2005). A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels. IEEE Journal of Solid-State Circuits. 40(12). 2646–2657. 79 indexed citations

Landman, P., et al.. (2003). A 62Gb/s backplane interconnect ASIC based on 3.1Gb/s serial-link technology. 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315). 1. 72–446. 18 indexed citations

Ramaswamy, S., et al.. (2003). Programmable termination for CML I/O's in high speed CMOS transceivers. 72–73. 1 indexed citations

Landman, P. & Jan M. Rabaey. (2002). Power estimation for high level synthesis. 361–366. 41 indexed citations

Landman, P., et al.. (2002). Compact inverse discrete cosine transform circuit for MPEG video decoding. assp 32. 364–373. 16 indexed citations

Landman, P.. (2002). High-level power estimation. 29–35. 67 indexed citations

10.

Landman, P., Hiroshi Takahashi, Hiroyuki Mizuno, et al.. (2002). A 1 V DSP for wireless communications. 92–93,. 11 indexed citations

11.

Landman, P., et al.. (1997). A 1V DSP for wireless communications. 97(315). 9–16. 3 indexed citations

12.

Landman, P., Hiroshi Takahashi, Hiroyuki Mizuno, et al.. (1997). A 1-V programmable DSP for wireless communications [CMOS]. IEEE Journal of Solid-State Circuits. 32(11). 1766–1776. 26 indexed citations

13.

Landman, P.. (1996). High-level power estimation. 29–35. 75 indexed citations

14.

Landman, P., R. Mehra, & Jan M. Rabaey. (1996). An integrated CAD environment for low-power design. IEEE Design & Test of Computers. 13(2). 72–82. 15 indexed citations

15.

Landman, P. & Jan M. Rabaey. (1996). Activity-sensitive architectural power analysis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 15(6). 571–587. 99 indexed citations

16.

Landman, P.. (1995). Low-power architectural design methodologies. 44 indexed citations

17.

Landman, P. & Jan M. Rabaey. (1995). Activity-sensitive architectural power analysis for the control path. 93–98. 38 indexed citations

18.

Landman, P. & Jan M. Rabaey. (1995). Architectural power analysis: The dual bit type method. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 3(2). 173–187. 263 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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