Uming Ko

733 total citations
20 papers, 438 citations indexed

About

Uming Ko is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Uming Ko has authored 20 papers receiving a total of 438 indexed citations (citations by other indexed papers that have themselves been cited), including 18 papers in Electrical and Electronic Engineering, 10 papers in Hardware and Architecture and 4 papers in Biomedical Engineering. Recurrent topics in Uming Ko's work include Low-power high-performance VLSI design (13 papers), Parallel Computing and Optimization Techniques (8 papers) and Advancements in Semiconductor Devices and Circuit Design (4 papers). Uming Ko is often cited by papers focused on Low-power high-performance VLSI design (13 papers), Parallel Computing and Optimization Techniques (8 papers) and Advancements in Semiconductor Devices and Circuit Design (4 papers). Uming Ko collaborates with scholars based in United States, Taiwan and Germany. Uming Ko's co-authors include Poras T. Balsara, Wai Lee, Gordon Gammie, H. Mair, Minh Quang Chau, D.B. Scott, Alice Wang, Anantha P. Chandrakasan, A. Wang and K. Heragu and has published in prestigious journals such as Proceedings of the IEEE, IEEE Journal of Solid-State Circuits and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

In The Last Decade

Uming Ko

18 papers receiving 407 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name	h						Papers	Cites
Uming Ko United States	10	395	158	117	58	44	20	438
Kaijian Shi United States	6	386 1.0×	198 1.3×	61 0.5×	72 1.2×	21 0.5×	14	433
H. Partovi United States	8	308 0.8×	132 0.8×	91 0.8×	59 1.0×	60 1.4×	19	342
Gary Yeap United States	8	267 0.7×	143 0.9×	46 0.4×	45 0.8×	38 0.9×	13	308
A. Chiba Japan	9	465 1.2×	142 0.9×	203 1.7×	64 1.1×	31 0.7×	11	532
H. Mair United States	5	256 0.6×	87 0.6×	93 0.8×	37 0.6×	18 0.4×	7	280
F. Minami Japan	9	390 1.0×	183 1.2×	77 0.7×	53 0.9×	16 0.4×	16	406
R.P. Preston United States	9	367 0.9×	242 1.5×	42 0.4×	127 2.2×	18 0.4×	13	475
Chung-Hsun Huang Taiwan	9	264 0.7×	80 0.5×	174 1.5×	55 0.9×	39 0.9×	29	334
M. Igarashi Japan	9	485 1.2×	196 1.2×	108 0.9×	96 1.7×	19 0.4×	12	527
G. Gerosa United States	8	428 1.1×	199 1.3×	107 0.9×	75 1.3×	25 0.6×	17	496

Countries citing papers authored by Uming Ko

Since Specialization

Citations

This map shows the geographic impact of Uming Ko's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Uming Ko with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Uming Ko more than expected).

Fields of papers citing papers by Uming Ko

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Uming Ko. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Uming Ko. The network helps show where Uming Ko may publish in the future.

Co-authorship network of co-authors of Uming Ko

This figure shows the co-authorship network connecting the top 25 collaborators of Uming Ko. A scholar is included among the top collaborators of Uming Ko based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Uming Ko. Uming Ko is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

Ko, Uming. (2016). Ultra-low power SoC for wearable & IoT. 1–1. 3 indexed citations

Ko, Uming. (2016). Ultra-low power SoC for wearable & loT. 1–1. 3 indexed citations

Ho, Stacy, et al.. (2016). Analog-digital partitioning and coupling in 3D-IC for RF applications. 1–4. 4 indexed citations

Park, Sunghyun, Alice Wang, Uming Ko, Li-Shiuan Peh, & Anantha P. Chandrakasan. (2016). Enabling Simultaneously Bi-Directional TSV Signaling for Energy and Area Efficient 3D-ICs. 163–168. 3 indexed citations

Wang, Alice, et al.. (2015). A vertical solenoid inductor for noise coupling minimization in 3D-IC. 55–58. 9 indexed citations

Ortmanns, Maurits, et al.. (2012). Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference. IEEE Journal of Solid-State Circuits. 48(1). 3–7. 2 indexed citations

Gammie, Gordon, Nathan Ickes, Mahmut E. Sinangil, et al.. (2011). A 28nm 0.6V low-power DSP for mobile applications. 132–134. 24 indexed citations

Gammie, Gordon, et al.. (2010). SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors. Proceedings of the IEEE. 98(2). 144–159. 29 indexed citations

Gammie, Gordon, Alice Wang, Minh Quang Chau, et al.. (2008). A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. 258–611. 58 indexed citations

10.

Mair, H., et al.. (2006). Leakage Power Reduction Techniques applied to 90-nm SoC Application Processor. 1–2. 1 indexed citations

11.

Mair, H., et al.. (2005). 90nm low leakage SoC design techniques for wireless applications. 138–140. 72 indexed citations

12.

Ko, Uming & Poras T. Balsara. (2002). High performance, energy efficient master-slave flip-flop circuits. 16–17. 4 indexed citations

13.

Ko, Uming & Poras T. Balsara. (2000). High-performance energy-efficient D-flip-flop circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 8(1). 94–98. 80 indexed citations

14.

Ko, Uming, et al.. (1997). Hybrid dual-threshold design techniques for high-performance processors with low-power features. 307–311. 12 indexed citations

15.

Ko, Uming, et al.. (1996). Design techniques for high performance, energy efficient control logic. 97–100. 11 indexed citations

16.

Ko, Uming, et al.. (1995). Low-power design techniques for high-performance CMOS adders. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 3(2). 327–333. 89 indexed citations

17.

Ko, Uming, et al.. (1995). Energy optimization of multi-level processor cache architectures. 45–49. 20 indexed citations

18.

Ko, Uming & Poras T. Balsara. (1995). Short-circuit power driven gate sizing technique for reducing power dissipation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 3(3). 450–455. 13 indexed citations

19.

Ko, Uming, et al.. (1992). A 0.65/spl mu/m 3.3-V CMOS gate array. 27.5.1–27.5.4. 1 indexed citations

20.

Ko, Uming, et al.. (1985). Contactless VLSI Laser Probing.. International Test Conference. 930–937.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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