H. Oyamatsu

546 total citations
26 papers, 316 citations indexed

About

H. Oyamatsu is a scholar working on Electrical and Electronic Engineering, Atomic and Molecular Physics, and Optics and Hardware and Architecture. According to data from OpenAlex, H. Oyamatsu has authored 26 papers receiving a total of 316 indexed citations (citations by other indexed papers that have themselves been cited), including 26 papers in Electrical and Electronic Engineering, 3 papers in Atomic and Molecular Physics, and Optics and 3 papers in Hardware and Architecture. Recurrent topics in H. Oyamatsu's work include Semiconductor materials and devices (21 papers), Advancements in Semiconductor Devices and Circuit Design (19 papers) and Integrated Circuits and Semiconductor Failure Analysis (7 papers). H. Oyamatsu is often cited by papers focused on Semiconductor materials and devices (21 papers), Advancements in Semiconductor Devices and Circuit Design (19 papers) and Integrated Circuits and Semiconductor Failure Analysis (7 papers). H. Oyamatsu collaborates with scholars based in Japan, South Korea and United States. H. Oyamatsu's co-authors include K. Sunouchi, F. Matsuoka, Atsushi Yamamoto, Jung Wook Park, Masayuki Yoshikawa, T. Nagase, K. Noma, Sung Joo Hong, Haruichi Kanaya and M. Kinugawa and has published in prestigious journals such as IEEE Transactions on Electron Devices, IEICE Transactions on Electronics and Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena.

In The Last Decade

H. Oyamatsu

22 papers receiving 299 citations

Peers

H. Oyamatsu
T. André United States
S. M. Alam United States
Hyuntaek Jung South Korea
K. Nagel Canada
C. Kothandaraman United States
Kyupil Lee South Korea
D. Moy United States
S. Lammers United States
R.C. Booth United Kingdom
Gitae Jeong South Korea
T. André United States
H. Oyamatsu
Citations per year, relative to H. Oyamatsu H. Oyamatsu (= 1×) peers T. André

Countries citing papers authored by H. Oyamatsu

Since Specialization
Citations

This map shows the geographic impact of H. Oyamatsu's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by H. Oyamatsu with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites H. Oyamatsu more than expected).

Fields of papers citing papers by H. Oyamatsu

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by H. Oyamatsu. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by H. Oyamatsu. The network helps show where H. Oyamatsu may publish in the future.

Co-authorship network of co-authors of H. Oyamatsu

This figure shows the co-authorship network connecting the top 25 collaborators of H. Oyamatsu. A scholar is included among the top collaborators of H. Oyamatsu based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with H. Oyamatsu. H. Oyamatsu is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Tsuchida, Kenji, et al.. (2017). 23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architecture. 396–397. 53 indexed citations
2.
Kishi, T., Jung Wook Park, Masayuki Yoshikawa, et al.. (2016). 4Gbit density STT-MRAM using perpendicular MTJ realized with compact cell structure. 27.1.1–27.1.4. 104 indexed citations
3.
Naito, Tomoyuki, et al.. (2010). World's first monolithic 3D-FPGA with TFT SRAM over 90nm 9 layer Cu CMOS. 219–220. 33 indexed citations
4.
Aikawa, H., et al.. (2009). Compact model for layout dependent variability. 1–4. 9 indexed citations
5.
Fukui, H., Hideaki� Yoshimura, H. Oyamatsu, et al.. (2005). Comprehensive study on layout dependence of soft errors in CMOS latch circuits and its scaling trend for 65 nm technology node and beyond. 40. 222–223. 6 indexed citations
6.
Inaba, S., K. Miyano, A. Hokazono, et al.. (2004). SODEL FET: Novel Channel and Source/Drain Profile Engineering Schemes by Selective Si Epitaxial Growth Technology. IEEE Transactions on Electron Devices. 51(9). 1401–1408. 3 indexed citations
7.
Oyamatsu, H., et al.. (2004). Advanced yield enhancement methodology for SoCs. 144–147. 3 indexed citations
8.
Morifuji, E., M. Kanda, Shôichi Matsuda, et al.. (2003). High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5). 655–658. 11 indexed citations
9.
Yamada, Takashi, Kenji Takahashi, H. Oyamatsu, et al.. (2003). An embedded DRAM technology on SOI/bulk hybrid substrate formed with SEG process for high-end SOC application. 112–113. 7 indexed citations
10.
11.
Igarashi, Hideji, H. Oyamatsu, Masahito Kodera, et al.. (2002). Manufacturable and reliable fluorine-doped low-k interlayer dielectric process for high performance logic LSI. 84–85.
12.
13.
Sakurai, Hiromu, Tomohiro Yamaguchi, Hiroshi Tomita, et al.. (2002). Copper contamination induced degradation of MOSFET characteristics and reliability. 26–27. 10 indexed citations
14.
Akasaka, Y., K. Nakajima, K. Suguro, et al.. (2002). W/WNx/poly-Si gate technology for future high speed deep submicron CMOS LSIs. 32. 497–500. 1 indexed citations
15.
16.
Oyamatsu, H., et al.. (1996). Design Methodology of Deep Submicron CMOS Devices for 1 V Operation (Special Issue on Low-Power LSI Technologies). IEICE Transactions on Electronics. 79(12). 1720–1725. 1 indexed citations
17.
Azuma, Tamiko, et al.. (1993). Nanofabrication techniques for a 100 nm-scale tungsten polycide gate structure. Journal of Vacuum Science & Technology B Microelectronics and Nanometer Structures Processing Measurement and Phenomena. 11(6). 2123–2126. 1 indexed citations
18.
Kinugawa, M., M. Kakumu, Takeshi Yoshida, et al.. (1990). TFT (thin film transistor) cell technology for 4 Mbit and more high density SRAMs. 23–24. 6 indexed citations
19.
Sawada, K., T. Takayanagi, K. Nogami, et al.. (1990). A 5 ns 369 kb port-configurable embedded SRAM with 0.5 mu m CMOS gate array. 226–227. 4 indexed citations
20.
Matsuoka, F., et al.. (1990). DRAIN STRUCTURE OPTIMIZATION FOR HIGHLY RELIABLE DEEP SUBMICRON nMOSFETs WITH 3.3V HIGH PERFORMANCE OPERATION ON THE SCALING TREND. 2 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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