Ching-Te Chuang

649 citations

35 papers · 525 indexed · h-index 9

Co-authors: Ming-Hsien Tu Shyh‐Jye Jou Ming-Chien Tsai Wei-Chiang Shih Pin Su Jae‐Joon Kim Vita Pi‐Ho Hu Ming-Long Fan
Topics: Advancements in Semiconductor Devices and Circuit Design (27 papers)Semiconductor materials and devices (23 papers)Low-power high-performance VLSI design (21 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Biomedical Engineering
Journals: IEEE Journal of Solid-State Circuits IEEE Transactions on Electron Devices IEEE Electron Device Letters
Partner nations: Taiwan United States

In The Last Decade

Ching-Te Chuang

34 papers receiving 498 citations

Peers

Countries citing papers authored by Ching-Te Chuang

Since Specialization

Citations

This map shows the geographic impact of Ching-Te Chuang's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ching-Te Chuang with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ching-Te Chuang more than expected).

Fields of papers citing papers by Ching-Te Chuang

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ching-Te Chuang. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ching-Te Chuang. The network helps show where Ching-Te Chuang may publish in the future.

Co-authorship network of co-authors of Ching-Te Chuang

This figure shows the co-authorship network connecting the top 25 collaborators of Ching-Te Chuang. A scholar is included among the top collaborators of Ching-Te Chuang based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ching-Te Chuang. Ching-Te Chuang is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Evaluation of analog performance of monolayer and bilayer two-dimensional transition metal dichalcogenide (TMD) MOSFETs 2017 ·(unknown),Chang-Hung Yu,Pin Su,Ching-Te Chuang	2
2	Impact of Random Variations on Cell Stability and Write-Ability of Low-Voltage SRAMs Using Monolayer and Bilayer Transition Metal Dichalcogenide (TMD) MOSFETs 2016 ·IEEE Electron Device Letters ·Chang-Hung Yu,Pin Su,Ching-Te Chuang	10
3	A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line 2016 ·Microelectronics Journal ·(unknown),(unknown),(unknown),(unknown),(unknown),(unknown),Ching-Te Chuang	6
4	All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction 2015 ·(unknown),Po-Tsang Huang,(unknown),(unknown),Ching-Te Chuang,Yuan‐Hua Chu,Wei Hwang	1
5	A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist 2014 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown),Ching-Te Chuang,Shyh‐Jye Jou,Ming-Hsien Tu,Yaping Wu,Chung-Ping Huang,(unknown),(unknown),(unknown),(unknown)	29
6	Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition 2014 ·(unknown),Po-Tsang Huang,(unknown),Kuan‐Neng Chen,Jin‐Chern Chiou,(unknown),(unknown),Ho‐Ming Tong,Ching-Te Chuang,Wei Hwang	8
7	Investigation of single-trap-induced random telegraph noise for tunnel FET based devices, 8T SRAM cell, and sense amplifiers 2013 ·Ming-Long Fan,Vita Pi‐Ho Hu,(unknown),Pin Su,Ching-Te Chuang	7
8	Near-/Sub-V<inf>th</inf> process, voltage, and temperature (PVT) sensors with dynamic voltage selection 2013 ·Ming‐Hung Chang,(unknown),(unknown),(unknown),Ching-Te Chuang,Kuan‐Neng Chen,Chen-Chao Wang,(unknown),(unknown),(unknown),Wei Hwang	8
9	A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing 2012 ·IEEE Journal of Solid-State Circuits ·Ming-Hsien Tu,(unknown),Ming-Chien Tsai,(unknown),(unknown),(unknown),(unknown),(unknown),Wei-Chiang Shih,Shyh‐Jye Jou,Ching-Te Chuang	147
10	Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist 2010 ·IEEE Transactions on Circuits and Systems I Regular Papers ·Ming-Hsien Tu,(unknown),Ming-Chien Tsai,Shyh‐Jye Jou,Ching-Te Chuang	110
11	Impact of NBTI and PBTI in SRAM bit-cells: Relative sensitivities and guidelines for application-specific target stability/performance 2009 ·Aditya Bansal,Rahul Rao,Jae‐Joon Kim,Sufi Zafar,J. H. Stathis,Ching-Te Chuang	28
12	Self-Repairing SRAM Using On-Chip Detection and Compensation 2009 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Niladri Narayan Mojumder,Saibal Mukhopadhyay,Jae‐Joon Kim,Ching-Te Chuang,Kaushik Roy	6
13	Yield estimation of SRAM circuits using "Virtual SRAM Fab" 2009 ·Aditya Bansal,(unknown),Rouwaida Kanj,Saibal Mukhopadhyay,(unknown),Erdem Acar,Amith Singhee,Keunwoo Kim,Ching-Te Chuang,Sani Nassif,(unknown),(unknown)	6
14	Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI 2007 ·Jie Deng,Keunwoo Kim,Ching-Te Chuang,H.‐S. Philip Wong	2
15	Power-Gating Schemes for Ultra-Thin SOI (UTSOI) Circuits in Hybrid SOI-Epitaxial CMOS Structures 2006 ·Shih-Hsien Lo,(unknown),Ching-Te Chuang,J.W. Sleight	1
16	Back-Gate Controlled READ SRAM with Improved Stability 2006 ·Jae‐Joon Kim,Keunwoo Kim,Ching-Te Chuang	6
17	Simulation of Nano-Scale Multi-Fingered PD/SOI MOSFETs Using the Boltzmann Transport Equation 2004 ·(unknown),Jayathi Y. Murthy,R. Viskanta,Rajiv Joshi,Ching-Te Chuang	2
18	PD/SOI SRAM performance in presence of gate-to-body tunneling current 2003 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·(unknown),Ching-Te Chuang,S.K.H. Fung,F. Assaderaghi,M. Sherony,Insoon Yang,G. Shahidi	1
19	SOI-optimized 64-bit high-speed CMOS adder design 2003 ·Jae‐Joon Kim,(unknown),Ching-Te Chuang,Kaushik Roy	5
20	Floating-body effects in partially depleted SOI CMOS circuits 1997 ·IEEE Journal of Solid-State Circuits ·Pong-Fei Lu,Ching-Te Chuang,(unknown),L. Wagner,(unknown),(unknown),(unknown),M.M. Pelella,S. Chu,C.J. Anderson	58

About Ching-Te Chuang

Ching-Te Chuang is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Biomedical Engineering, having authored 35 papers that have together received 525 indexed citations. Recurring topics across this work include Advancements in Semiconductor Devices and Circuit Design (27 papers), Semiconductor materials and devices (23 papers) and Low-power high-performance VLSI design (21 papers). The work is most often cited by research in Hardware and Architecture (112 citations), Electrical and Electronic Engineering (510 citations) and Biomedical Engineering (43 citations). Ching-Te Chuang has collaborated with scholars based in Taiwan and United States. Frequent co-authors include Ming-Hsien Tu, Shyh‐Jye Jou, Ming-Chien Tsai, Wei-Chiang Shih, Pin Su, Jae‐Joon Kim, Vita Pi‐Ho Hu, Ming-Long Fan, M.M. Pelella and Aditya Bansal. Their work appears in journals such as IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices and IEEE Electron Device Letters.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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