Ming-Chien Tsai

413 total citations
11 papers, 325 citations indexed

About

Ming-Chien Tsai is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, Ming-Chien Tsai has authored 11 papers receiving a total of 325 indexed citations (citations by other indexed papers that have themselves been cited), including 11 papers in Electrical and Electronic Engineering, 3 papers in Hardware and Architecture and 2 papers in Biomedical Engineering. Recurrent topics in Ming-Chien Tsai's work include Low-power high-performance VLSI design (6 papers), Semiconductor materials and devices (5 papers) and Advancements in PLL and VCO Technologies (5 papers). Ming-Chien Tsai is often cited by papers focused on Low-power high-performance VLSI design (6 papers), Semiconductor materials and devices (5 papers) and Advancements in PLL and VCO Technologies (5 papers). Ming-Chien Tsai collaborates with scholars based in Taiwan, Australia and United States. Ming-Chien Tsai's co-authors include Shyh‐Jye Jou, Ming-Hsien Tu, Ching-Te Chuang, Wei-Chiang Shih, Ching-Hwa Cheng, D. Boerstler, Ching-Te Chuang, H. Peter Hofstee, Yu-Cherng Hung and Yi-Wei Lin and has published in prestigious journals such as Journal of The Electrochemical Society, IEEE Journal of Solid-State Circuits and IBM Journal of Research and Development.

In The Last Decade

Ming-Chien Tsai

11 papers receiving 311 citations

Peers

Countries citing papers authored by Ming-Chien Tsai

Since Specialization

Citations

This map shows the geographic impact of Ming-Chien Tsai's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Ming-Chien Tsai with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Ming-Chien Tsai more than expected).

Fields of papers citing papers by Ming-Chien Tsai

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Ming-Chien Tsai. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Ming-Chien Tsai. The network helps show where Ming-Chien Tsai may publish in the future.

Co-authorship network of co-authors of Ming-Chien Tsai

This figure shows the co-authorship network connecting the top 25 collaborators of Ming-Chien Tsai. A scholar is included among the top collaborators of Ming-Chien Tsai based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Ming-Chien Tsai. Ming-Chien Tsai is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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11 of 11 papers shown

#	Work	Indexed citations
1	True hardware random number generation implemented in the 32-nm SOI POWER7+ processor 2013 ·IBM Journal of Research and Development ·(unknown), (unknown), D. Boerstler, (unknown), (unknown), H. Peter Hofstee, (unknown), Ming-Chien Tsai	12
2	A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing 2012 ·IEEE Journal of Solid-State Circuits ·Ming-Hsien Tu, (unknown), Ming-Chien Tsai, (unknown), (unknown), (unknown), (unknown), (unknown), Wei-Chiang Shih, Shyh‐Jye Jou, Ching-Te Chuang	147
3	An all-digital bit transistor characterization scheme for CMOS 6T SRAM array 2012 ·(unknown), Shao-Cheng Wang, Yi-Wei Lin, Ming-Chien Tsai, Ching-Te Chuang, Shyh‐Jye Jou, (unknown), Wei-Chiang Shih, (unknown), (unknown)	2
4	Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array 2012 ·Ming-Chien Tsai, Yi-Wei Lin, (unknown), Ming-Hsien Tu, Wei-Chiang Shih, (unknown), (unknown), Shyh‐Jye Jou, Ching-Te Chuang, Wei Hwang	4
5	Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM 2012 ·Shao-Cheng Wang, (unknown), Yi-Wei Lin, Ming-Chien Tsai, (unknown), Shyh‐Jye Jou, Ching-Te Chuang, (unknown), Wei-Chiang Shih, (unknown), (unknown)	3
6	Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist 2010 ·IEEE Transactions on Circuits and Systems I Regular Papers ·Ming-Hsien Tu, (unknown), Ming-Chien Tsai, Shyh‐Jye Jou, Ching-Te Chuang	110
7	Preparation and Electrochemical Performance of Externally Doped Sulfonated Polyaniline/Multiwalled Carbon Nanotube Composites 2009 ·Journal of The Electrochemical Society ·Yen‐Wen Lin, Hao‐Hsiang Chang, Yushan Liu, Ming-Chien Tsai, Yu-Chen Tsai, Tzong‐Ming Wu	6
8	A full-synthesizable high-precision built-in delay time measurement circuit 2009 ·Ming-Chien Tsai, Ching-Hwa Cheng	1
9	Asymmetrical Write-assist for single-ended SRAM operation 2009 ·(unknown), Ming-Hsien Tu, Ming-Chien Tsai, Shyh‐Jye Jou, Ching-Te Chuang	6
10	An All-Digital High-Precision Built-In Delay Time Measurement Circuit 2008 ·Ming-Chien Tsai, Ching-Hwa Cheng, (unknown)	32
11	High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability 2006 ·(unknown), (unknown), Yu-Cherng Hung, Ming-Chien Tsai	2

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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