C. Visweswariah

2.1k citations

28 papers · 1.6k indexed · 1 hit paper · h-index 16

Electrical and Electronic Engineering top 2%
Hardware and Architecture top 0.5%
Biomedical Engineering
Computational Theory and Mathematics top 5%
Statistics, Probability and Uncertainty top 5%

Co-authors: Kerim Kalafala S.G. Walker Kaushik Ravindran L.T. Pillage Ronald A. Rohrer R.A. Rohrer J.A.G. Jess Srinath R. Naidu
Topics: Low-power high-performance VLSI design (24 papers)VLSI and FPGA Design Techniques (18 papers)VLSI and Analog Circuit Testing (12 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Statistics, Probability and Uncertainty
Journals: IBM Journal of Research and Development IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Circuits and Devices Magazine
Partner nations: United States Netherlands Ireland

In The Last Decade

C. Visweswariah

27 papers receiving 1.5k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

First-order incremental block-based statistical timing analysis

2004 514 citations C. Visweswariah, Kaushik Ravindran et al. profile →

Peers

Countries citing papers authored by C. Visweswariah

Since Specialization

Citations

This map shows the geographic impact of C. Visweswariah's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by C. Visweswariah with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites C. Visweswariah more than expected).

Fields of papers citing papers by C. Visweswariah

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by C. Visweswariah. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by C. Visweswariah. The network helps show where C. Visweswariah may publish in the future.

Co-authorship network of co-authors of C. Visweswariah

This figure shows the co-authorship network connecting the top 25 collaborators of C. Visweswariah. A scholar is included among the top collaborators of C. Visweswariah based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with C. Visweswariah. C. Visweswariah is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work	Indexed citations
1	Managing uncertainty in electricity generation and demand forecasting 2016 ·IBM Journal of Research and Development ·Kevin M. Warren,(unknown),(unknown),Yanan Fu,Shibani Ghosh,Dzung T. Phan,Mathieu Sinn,(unknown),C. Visweswariah	9
2	Optimal Test Margin Computation for At-Speed Structural Test 2009 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Jinjun Xiong,V. Zolotov,C. Visweswariah,Peter Habitz	8
3	First-Order Incremental Block-Based Statistical Timing Analysis 2006 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·C. Visweswariah,Kaushik Ravindran,Kerim Kalafala,S.G. Walker,(unknown),(unknown),(unknown),N. Venkateswaran,Jeffrey G. Hemmett	185
4	Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits 2006 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·J.A.G. Jess,Kerim Kalafala,Srinath R. Naidu,Ria Otten,C. Visweswariah	21
5	Criticality computation in parameterized statistical timing 2006 ·Proceedings - ACM IEEE Design Automation Conference ·Jinjun Xiong,V. Zolotov,N. Venkateswaran,C. Visweswariah	11
6	Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions 2005 ·(unknown),V. Zolotov,(unknown),C. Visweswariah	12
7	Death, taxes and failing chips 2004 ·C. Visweswariah	52
8	First-order incremental block-based statistical timing analysisbreakdown → 2004 ·C. Visweswariah,Kaushik Ravindran,Kerim Kalafala,S.G. Walker,(unknown)	514
9	Piecewise approximate circuit simulation 2003 ·C. Visweswariah,R.A. Rohrer	4
10	Statistical timing for parametric yield prediction of digital integrated circuits 2003 ·J.A.G. Jess,Kerim Kalafala,Srinath R. Naidu,Ria Otten,C. Visweswariah	105
11	Optimization of custom MOS circuits by transistor sizing 2002 ·Andrew R. Conn,(unknown),R.A. Haring,(unknown),C. Visweswariah	26
12	Uncertainty-aware circuit optimization 2002 ·Xiaoliang Bai,C. Visweswariah,(unknown),(unknown)	41
13	Incorporation of inductors in piecewise approximate circuit simulation 2002 ·C. Visweswariah,P. Feldmann,R.A. Rohrer	0
14	Noise considerations in circuit optimization 2000 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·C. Visweswariah,R.A. Haring,Andrew R. Conn	12
15	Gradient-based optimization of custom circuits using a static-timing formulation 1999 ·Andrew R. Conn,Ibrahim M. Elfadel,W. W. Molzen,P.R. O'Brien,Philip N. Strenski,C. Visweswariah,(unknown)	31
16	Electronic Circuit and System Simulation Methods [Book Reviews] 1998 ·IEEE Circuits and Devices Magazine ·L.T. Pillage,R.A. Rohrer,C. Visweswariah	16
17	Incremental event-driven simulation of digital FET circuits 1993 ·C. Visweswariah,(unknown)	8
18	M/sup 3/-a multilevel mixed-mode mixed A/D simulator 1992 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Rakesh Chadha,C. Visweswariah,(unknown)	12
19	Efficient simulation of bipolar digital ICs 1991 ·C. Visweswariah,Ronald A. Rohrer	1
20	Model development and verification for high level analog blocks 1988 ·Design Automation Conference ·C. Visweswariah,Rakesh Chadha,(unknown)	23

About C. Visweswariah

C. Visweswariah is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Statistics, Probability and Uncertainty, having authored 28 papers that have together received 1.6k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (24 papers), VLSI and FPGA Design Techniques (18 papers) and VLSI and Analog Circuit Testing (12 papers). The work is most often cited by research in Hardware and Architecture (953 citations), Electrical and Electronic Engineering (1.5k citations) and Statistics, Probability and Uncertainty (67 citations). C. Visweswariah has collaborated with scholars based in United States, Netherlands and Ireland. Frequent co-authors include Kerim Kalafala, S.G. Walker, Kaushik Ravindran, L.T. Pillage, Ronald A. Rohrer, R.A. Rohrer, J.A.G. Jess, Srinath R. Naidu, N. Venkateswaran and Ria Otten. Their work appears in journals such as IBM Journal of Research and Development, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems and IEEE Circuits and Devices Magazine.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

Explore authors with similar magnitude of impact