V. Visvanathan

1.0k total citations
56 papers, 784 citations indexed

About

V. Visvanathan is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Biomedical Engineering. According to data from OpenAlex, V. Visvanathan has authored 56 papers receiving a total of 784 indexed citations (citations by other indexed papers that have themselves been cited), including 37 papers in Electrical and Electronic Engineering, 25 papers in Hardware and Architecture and 13 papers in Biomedical Engineering. Recurrent topics in V. Visvanathan's work include Low-power high-performance VLSI design (22 papers), VLSI and Analog Circuit Testing (15 papers) and Analog and Mixed-Signal Circuit Design (13 papers). V. Visvanathan is often cited by papers focused on Low-power high-performance VLSI design (22 papers), VLSI and Analog Circuit Testing (15 papers) and Analog and Mixed-Signal Circuit Design (13 papers). V. Visvanathan collaborates with scholars based in India, United States and Netherlands. V. Visvanathan's co-authors include Linda Milor, Pradip Kumar Mandal, P. Sadayappan, Alberto Sangiovanni‐Vincentelli, Pradip Mandal, Bharadwaj Amrutur, H. S. Jamadagni, N.V. Arvind, Bishnu Prasad Das and S. Ramanathan and has published in prestigious journals such as IEEE Transactions on Computers, Signal Processing and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

V. Visvanathan

50 papers receiving 744 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
V. Visvanathan India 14 666 471 142 74 57 56 784
C. Visweswariah United States 16 1.5k 2.2× 953 2.0× 124 0.9× 99 1.3× 32 0.6× 28 1.6k
Guy Bois Canada 11 293 0.4× 315 0.7× 29 0.2× 114 1.5× 30 0.5× 80 568
T. Chen United States 11 336 0.5× 196 0.4× 70 0.5× 29 0.4× 15 0.3× 46 494
Kei-Yong Khoo United States 13 608 0.9× 403 0.9× 77 0.5× 76 1.0× 20 0.4× 51 717
Yiyu Shi United States 15 588 0.9× 211 0.4× 29 0.2× 51 0.7× 29 0.5× 68 689
Vladimir Zolotov United States 23 2.0k 3.0× 1.4k 3.0× 136 1.0× 56 0.8× 19 0.3× 74 2.1k
M. Renovell France 27 2.0k 3.0× 1.8k 3.9× 247 1.7× 35 0.5× 104 1.8× 179 2.1k
Tsin‐Yuan Chang Taiwan 15 583 0.9× 226 0.5× 236 1.7× 179 2.4× 29 0.5× 46 823
Tan‐Li Chou United States 16 755 1.1× 470 1.0× 46 0.3× 31 0.4× 10 0.2× 28 855
Georgios Zervakis Greece 17 685 1.0× 243 0.5× 154 1.1× 91 1.2× 16 0.3× 49 852

Countries citing papers authored by V. Visvanathan

Since Specialization
Citations

This map shows the geographic impact of V. Visvanathan's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by V. Visvanathan with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites V. Visvanathan more than expected).

Fields of papers citing papers by V. Visvanathan

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by V. Visvanathan. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by V. Visvanathan. The network helps show where V. Visvanathan may publish in the future.

Co-authorship network of co-authors of V. Visvanathan

This figure shows the co-authorship network connecting the top 25 collaborators of V. Visvanathan. A scholar is included among the top collaborators of V. Visvanathan based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with V. Visvanathan. V. Visvanathan is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
Karthikeyan, P., et al.. (2023). Investigating the impact of variable aspect ratio cathode flow field on temperature distribution and performance in a PEM fuel cell. Numerical Heat Transfer Part A Applications. 86(3). 588–612. 1 indexed citations
2.
Visvanathan, V., et al.. (2013). Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. Journal of Low Power Electronics. 9(2). 207–228. 2 indexed citations
3.
Pasumarthi, Rama Kumar, et al.. (2012). Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. Journal of Low Power Electronics. 8(5). 684–695. 1 indexed citations
4.
Visvanathan, V., et al.. (2008). Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. Journal of Low Power Electronics. 4(3). 301–319. 1 indexed citations
5.
Ramanathan, S., et al.. (2005). A Methodology for Generating Application Specific Tree Multipliers. 176–179. 1 indexed citations
6.
Visvanathan, V., et al.. (2005). A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries. 530–535. 3 indexed citations
7.
Mandal, Pradip & V. Visvanathan. (2002). Macromodeling of the AC characteristics of CMOS op-amps. 334–340. 1 indexed citations
8.
Ramanathan, S. & V. Visvanathan. (2002). A systolic architecture for LMS adaptive filtering with minimal adaptation delay. 286–289. 9 indexed citations
9.
Mandal, Pradip & V. Visvanathan. (2002). A self-biased high performance folded cascode CMOS op-amp. 429–434. 31 indexed citations
10.
Mandal, Pradip & V. Visvanathan. (2002). Design of high performance two stage CMOS cascode op-amps with stable biasing. 234–237. 2 indexed citations
11.
Mandal, Pradip Kumar & V. Visvanathan. (2001). CMOS op-amp sizing using a geometric programming formulation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 20(1). 22–38. 129 indexed citations
12.
Visvanathan, V., et al.. (1999). Statistical device models from worst case files and electrical test data. IEEE Transactions on Semiconductor Manufacturing. 12(4). 470–484. 33 indexed citations
13.
Ramanathan, S., V. Visvanathan, & S. K. Nandy. (1999). Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. The Journal of VLSI Signal Processing Systems for Signal Image and Video Technology. 22(3). 173–195. 4 indexed citations
14.
Ramanathan, S., V. Visvanathan, & S. K. Nandy. (1999). Synthesis of ASIPs for DSP algorithms. Integration. 28(1). 13–32. 3 indexed citations
15.
Mandal, Pradip Kumar & V. Visvanathan. (1999). A new approach for CMOS op-amp synthesis. 7. 189–194. 4 indexed citations
16.
Mandal, Pradip & V. Visvanathan. (1993). Macromodeling of the A.C. characteristics of CMOS Op-amps. International Conference on Computer Aided Design. 334–340. 8 indexed citations
17.
Somasekhar, Dinesh & V. Visvanathan. (1993). A 230 MHz Half Bit Level Pipelined Multiplier using True Single Phase Clocking. sc 24. 347–350. 3 indexed citations
18.
Sadayappan, P., et al.. (1991). Multifrontal Factorization of Sparse Matrices on Shared-Memory Multiprocessors.. Proceedings of the International Conference on Parallel Processing. 159–166. 5 indexed citations
19.
Milor, Linda & V. Visvanathan. (1989). Detection of catastrophic faults in analog integrated circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 8(2). 114–130. 206 indexed citations
20.
Sadayappan, P. & V. Visvanathan. (1989). Efficient sparse matrix factorization for circuit simulation on vector supercomputers. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 8(12). 1276–1285. 13 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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