V. Visvanathan

1.0k citations

56 papers · 784 · h-index 14

Impact in

Hardware and Architecture top 1%
- VLSI and Analog Circuit Testing
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 5%
- VLSI and FPGA Design Techniques
- Low-power high-performance VLSI design
- Integrated Circuits and Semiconductor Failure Analysis
- Advancements in Semiconductor Devices and Circuit Design
- Semiconductor materials and devices

Papers in

Electrical and Electronic Engineering 37
- Low-power high-performance VLSI design 22
- VLSI and FPGA Design Techniques 12
- Advancements in Semiconductor Devices and Circuit Design 11
Hardware and Architecture 25
- VLSI and Analog Circuit Testing 15
- Parallel Computing and Optimization Techniques 10

Co-authors: Linda Milor (2 shared papers)Pradip Kumar Mandal (3 shared papers)P. Sadayappan (7 shared papers)Alberto Sangiovanni‐Vincentelli (3 shared papers)Pradip Mandal (4 shared papers)Bharadwaj Amrutur (4 shared papers)N.V. Arvind (4 shared papers)H. S. Jamadagni (4 shared papers)
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (5 papers)IEEE Transactions on Semiconductor Manufacturing (3 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (1 paper)Signal Processing (1 paper)IEEE Circuits and Devices Magazine (1 paper)
Partner nations: India United States Netherlands

In The Last Decade

V. Visvanathan

50 papers receiving 744 citations

Peers

Countries citing papers authored by V. Visvanathan

Since Specialization

Citations

This map shows the geographic impact of V. Visvanathan's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by V. Visvanathan with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites V. Visvanathan more than expected).

Fields of papers citing papers by V. Visvanathan

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by V. Visvanathan. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by V. Visvanathan. The network helps show where V. Visvanathan may publish in the future.

Co-authors

The 25 scholars most cited alongside V. Visvanathan, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with V. Visvanathan Line = papers co-authored together V. Visvanathan links everyone, so they are left out of the graph.

All Works

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20 of 20 papers shown

Showing the 20 most-cited of 56 papers — load more, or switch the sort, to bring in the rest.

#	Work
1	Detection of catastrophic faults in analog integrated circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Linda Milor, V. Visvanathan	1989	206
2	CMOS op-amp sizing using a geometric programming formulation IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Pradip Kumar Mandal, V. Visvanathan	2001	129
3	Striving for small-signal stability IEEE Circuits and Devices Magazine ·Mengliang Tian, V. Visvanathan, J.C. Hantgan, K. Kundert	2001	38
4	Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator IEEE Transactions on Semiconductor Manufacturing ·Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N.V. Arvind, V. Visvanathan	2009	37
5	Statistical device models from worst case files and electrical test data IEEE Transactions on Semiconductor Manufacturing ·K. Singhal, V. Visvanathan	1999	33
6	Circuit simulation on shared-memory multiprocessors IEEE Transactions on Computers ·P. Sadayappan, V. Visvanathan	1988	32
7	A self-biased high performance folded cascode CMOS op-amp Pradip Mandal, V. Visvanathan	2002	31
8	Diagnosability of nonlinear circuits and systems-Part I: The dc case IEEE Transactions on Circuits and Systems ·V. Visvanathan, Alberto Sangiovanni‐Vincentelli	1981	27
9	Within-die gate delay variability measurement using re-configurable ring oscillator Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N.V. Arvind, V. Visvanathan	2008	22
10	Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·V. Janakiraman, Bharadwaj Amrutur, V. Visvanathan	2010	20
11	A 230-MHz half-bit level pipelined multiplier using true single-phase clocking IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Dinesh Somasekhar, V. Visvanathan	1993	19
12	Diagnosability of nonlinear circuits and systems-Part II: Dynamical systems IEEE Transactions on Circuits and Systems ·R. Saeks, Alberto Sangiovanni‐Vincentelli, V. Visvanathan	1981	18
13	A Computational Approach for the Diagnosability of Dynamical Circuits IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·V. Visvanathan, Alberto Sangiovanni‐Vincentelli	1984	16
14	The Center Design Optimization System AT&T Technical Journal ·Kishore Singhal, Colin C. McAndrew, Sani Nassif, V. Visvanathan	1989	14
15	Efficient sparse matrix factorization for circuit simulation on vector supercomputers IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·P. Sadayappan, V. Visvanathan	1989	13
16	Sequentially linear fault diagnosis: Part I-Theory IEEE Transactions on Circuits and Systems ·Ruey‐Wen Liu, V. Visvanathan	1979	10
17	Voltage and Temperature-Aware SSTA Using Neural Network Delay Model IEEE Transactions on Semiconductor Manufacturing ·Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N.V. Arvind, V. Visvanathan	2011	10
18	A systolic architecture for LMS adaptive filtering with minimal adaptation delay S. Ramanathan, V. Visvanathan	2002	9
19	Macromodeling of the A.C. characteristics of CMOS Op-amps International Conference on Computer Aided Design ·Pradip Mandal, V. Visvanathan	1993	8
20	Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay Integration ·S. Ramanathan, V. Visvanathan	1999	7

About V. Visvanathan

V. Visvanathan is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture, Biomedical Engineering, Signal Processing and Computational Theory and Mathematics, having authored 56 papers that have together received 784 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (22 papers), VLSI and Analog Circuit Testing (15 papers), Analog and Mixed-Signal Circuit Design (13 papers), VLSI and FPGA Design Techniques (12 papers), Advancements in Semiconductor Devices and Circuit Design (11 papers), Parallel Computing and Optimization Techniques (10 papers), Digital Filter Design and Implementation (7 papers) and Matrix Theory and Algorithms (6 papers). The work is most often cited by research in Hardware and Architecture (471 citations), Electrical and Electronic Engineering (666 citations), Computational Theory and Mathematics (74 citations), Computational Mathematics (2 citations) and Biomedical Engineering (142 citations). V. Visvanathan has collaborated with scholars based in India, United States and Netherlands. Frequent co-authors include Linda Milor, Pradip Kumar Mandal, P. Sadayappan, Alberto Sangiovanni‐Vincentelli, Pradip Mandal, Bharadwaj Amrutur, N.V. Arvind, H. S. Jamadagni, Bishnu Prasad Das and S. Ramanathan. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Semiconductor Manufacturing, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Signal Processing and IEEE Circuits and Devices Magazine.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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