V. Zolotov

1.4k citations

39 papers · 1.1k indexed · h-index 18

Co-authors: David Blaauw A. Agarwal Rajesh Panda Matthew R. Guthaus Savithri Sundareswaran Chanhee Oh C. Visweswariah Chang-Hwan Oh
Topics: Low-power high-performance VLSI design (32 papers)VLSI and Analog Circuit Testing (25 papers)VLSI and FPGA Design Techniques (22 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Statistics, Probability and Uncertainty
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Transactions on Very Large Scale Integration (VLSI) SystemsIzvestiya of Saratov University Mathematics Mechanics Informatics
Partner nations: United States Russia

In The Last Decade

V. Zolotov

39 papers receiving 1.0k citations

Peers

Countries citing papers authored by V. Zolotov

Since Specialization

Citations

This map shows the geographic impact of V. Zolotov's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by V. Zolotov with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites V. Zolotov more than expected).

Fields of papers citing papers by V. Zolotov

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by V. Zolotov. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by V. Zolotov. The network helps show where V. Zolotov may publish in the future.

Co-authorship network of co-authors of V. Zolotov

This figure shows the co-authorship network connecting the top 25 collaborators of V. Zolotov. A scholar is included among the top collaborators of V. Zolotov based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with V. Zolotov. V. Zolotov is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Construction of 3D solid vertebral models using convolutional neural networks 2021 ·Izvestiya of Saratov University Mathematics Mechanics Informatics ·(unknown),(unknown),(unknown),V. Zolotov,(unknown),И. В. Кириллова,(unknown)	2
2	Constructing the dependence between the Young’s modulus value and the Hounsfield units of spongy tissue of human femoral heads 2021 ·Izvestiya of Saratov University Mathematics Mechanics Informatics ·(unknown),(unknown),(unknown),(unknown),V. Zolotov,(unknown),И. В. Кириллова,(unknown),(unknown),(unknown),(unknown)	3
3	Optimal Test Margin Computation for At-Speed Structural Test 2009 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Jinjun Xiong,V. Zolotov,C. Visweswariah,Peter Habitz	8
4	Criticality computation in parameterized statistical timing 2006 ·Proceedings - ACM IEEE Design Automation Conference ·Jinjun Xiong,V. Zolotov,N. Venkateswaran,C. Visweswariah	11
5	Discrete Vt assignment and gate sizing using a self-snapping continuous formulation 2005 ·International Conference on Computer Aided Design ·Sagar Shah,Ashish Srivastava,Dinesh Sharma,Dennis Sylvester,David Blaauw,V. Zolotov	35
6	Gate sizing using incremental parameterized statistical timing analysis 2005 ·International Conference on Computer Aided Design ·Matthew R. Guthaus,(unknown),(unknown),V. Zolotov	63
7	Optimal placement of power-supply pads and pins 2005 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·Min Zhao,Yuhong Fu,V. Zolotov,Savithri Sundareswaran,Rajesh Panda	12
8	Delay noise pessimism reduction by logic correlations 2005 ·(unknown),S. V. Gavrilov,(unknown),V. Zolotov,(unknown),Chang-Hwan Oh,Rajesh Panda	10
9	Pessimism reduction in crosstalk noise aware STA 2005 ·(unknown),V. Zolotov,Rajesh Panda,(unknown),(unknown),(unknown),Chang-Hwan Oh	11
10	False-noise analysis for domino circuits 2004 ·Design, Automation, and Test in Europe ·(unknown),S. V. Gavrilov,V. Zolotov,Chanhee Oh,Rajesh Panda,(unknown)	1
11	Static electromigration analysis for signal interconnects 2004 ·Chanhee Oh,David Blaauw,(unknown),V. Zolotov,Rajesh Panda,(unknown)	4
12	Statistical Clock Skew Analysis Considering Intradie-Process Variations 2004 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·A. Agarwal,V. Zolotov,David Blaauw	23
13	Statistical timing analysis using bounds and selective enumeration 2003 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·A. Agarwal,V. Zolotov,David Blaauw	119
14	Fast on-chip inductance simulation using a precorrected-FFT method 2003 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown),David Blaauw,V. Zolotov,Kaushik Gala,Min Zhao,Rajesh Panda,Sachin S. Sapatnekar	8
15	Statistical timing analysis using bounds [IC verification] 2003 ·2003 Design, Automation and Test in Europe Conference and Exhibition ·A. Agarwal,David Blaauw,V. Zolotov,Sarma Vrudhula	18
16	Analysis of noise avoidance techniques in DSM interconnects using a complete crosstalk noise model 2003 ·(unknown),David Blaauw,V. Zolotov,Rajesh Panda,I.N. Hajj	34
17	Statistical delay computation considering spatial correlations 2003 ·A. Agarwal,David Blaauw,V. Zolotov,Savithri Sundareswaran,Min Zhao,Kaushik Gala,Rajesh Panda	52
18	Inductance model and analysis methodology for high-speed on-chip interconnect 2002 ·IEEE Transactions on Very Large Scale Integration (VLSI) Systems ·Kaushik Gala,David Blaauw,V. Zolotov,Pravin M. Vaidya,(unknown)	9
19	Slope propagation in static timing analysis 2002 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·David Blaauw,V. Zolotov,Savithri Sundareswaran	32
20	Model and analysis for combined package and on-chip power grid simulation 2000 ·Rajesh Panda,David Blaauw,(unknown),V. Zolotov,(unknown),(unknown)	30

About V. Zolotov

V. Zolotov is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Statistics, Probability and Uncertainty, having authored 39 papers that have together received 1.1k indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (32 papers), VLSI and Analog Circuit Testing (25 papers) and VLSI and FPGA Design Techniques (22 papers). The work is most often cited by research in Hardware and Architecture (661 citations), Electrical and Electronic Engineering (1.0k citations) and Statistics, Probability and Uncertainty (20 citations). V. Zolotov has collaborated with scholars based in United States and Russia. Frequent co-authors include David Blaauw, A. Agarwal, Rajesh Panda, Matthew R. Guthaus, Savithri Sundareswaran, Chanhee Oh, C. Visweswariah, Chang-Hwan Oh, N. Venkateswaran and Kaushik Gala. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and Izvestiya of Saratov University Mathematics Mechanics Informatics.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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