Kerim Kalafala
- Hardware and Architecture top 1%
- VLSI and Analog Circuit Testing 4
- Parallel Computing and Optimization Techniques 1
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- Low-power high-performance VLSI design 8
- VLSI and FPGA Design Techniques 6
- Semiconductor materials and devices 2
- Electromagnetic Compatibility and Noise Suppression 1
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- Probabilistic and Robust Engineering Design 2
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- Interconnection Networks and Systems 1
Kerim Kalafala
9 papers receiving 844 citations
Hit Papers
Peers
Comparison fields: 5 of 26
- Hardware and Architecture 638
- Electrical and Electronic Engineering 824
- Statistics, Probability and Uncertainty 46
- Computational Theory and Mathematics 38
- Computer Networks and Communications 50
Countries citing papers authored by Kerim Kalafala
This map shows the geographic impact of Kerim Kalafala's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Kerim Kalafala with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Kerim Kalafala more than expected).
Fields of papers citing papers by Kerim Kalafala
This network shows the impact of papers produced by Kerim Kalafala. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Kerim Kalafala. The network helps show where Kerim Kalafala may publish in the future.
Co-authorship network
The 16 scholars most cited alongside Kerim Kalafala, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.
All Works
| # | Work | ||
|---|---|---|---|
| 1 | 2016 | 24 | |
| 2 | 2016 | 2 | |
| 3 | 2010 | 2 | |
| 4 | A Hierarchical Transistor and Gate-Level Statistical Timing Flow for Microprocessor Designs | 2009 | 4 |
| 5 | 2006 | 185 | |
| 6 | 2006 | 21 | |
| 7 | First-order incremental block-based statistical timing analysisbreakdown → | 2004 | 514 |
| 8 | 2003 | 105 | |
| 9 | 2003 | 41 |
About Kerim Kalafala
Kerim Kalafala is a scholar working on Hardware and Architecture, Statistics, Probability and Uncertainty and Electrical and Electronic Engineering, having authored 9 papers that have together received 898 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (8 papers), VLSI and FPGA Design Techniques (6 papers), VLSI and Analog Circuit Testing (4 papers), Probabilistic and Robust Engineering Design (2 papers), Semiconductor materials and devices (2 papers), Interconnection Networks and Systems (1 paper), Electromagnetic Compatibility and Noise Suppression (1 paper) and Parallel Computing and Optimization Techniques (1 paper). The work is most often cited by research in Hardware and Architecture (638 citations), Electrical and Electronic Engineering (824 citations) and Statistics, Probability and Uncertainty (46 citations). Kerim Kalafala has collaborated with scholars based in United States and Netherlands. Frequent co-authors include C. Visweswariah, S.G. Walker, Kaushik Ravindran, J.A.G. Jess, Srinath R. Naidu, Ria Otten, N. Venkateswaran, Jeffrey G. Hemmett, Debjit Sinha and Martin D. F. Wong. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.