Yici Cai
- Electrical and Electronic Engineering top 2%
- Hardware and Architecture top 0.5%
- Computer Networks and Communications top 5%
- Computational Theory and Mathematics top 5%
- Biomedical Engineering
- Topics
- VLSI and FPGA Design Techniques (142 papers)Low-power high-performance VLSI design (99 papers)VLSI and Analog Circuit Testing (76 papers)
- Cited by
- Hardware and ArchitectureElectrical and Electronic EngineeringStatistics, Probability and Uncertainty
- Journals
- IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsIEEE Transactions on Circuits and Systems I Regular PapersIEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Partner nations
- ChinaUnited StatesHong Kong
In The Last Decade
Yici Cai
205 papers receiving 1.6k citations
Peers
Comparison fields: 5 of 58
- Electrical and Electronic Engineering 1.5k
- Hardware and Architecture 826
- Computer Networks and Communications 196
- Computational Theory and Mathematics 133
- Biomedical Engineering 131
Countries citing papers authored by Yici Cai
This map shows the geographic impact of Yici Cai's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yici Cai with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yici Cai more than expected).
Fields of papers citing papers by Yici Cai
This network shows the impact of papers produced by Yici Cai. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yici Cai. The network helps show where Yici Cai may publish in the future.
Co-authorship network of co-authors of Yici Cai
This figure shows the co-authorship network connecting the top 25 collaborators of Yici Cai. A scholar is included among the top collaborators of Yici Cai based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yici Cai. Yici Cai is excluded from the visualization to improve readability, since they are connected to all nodes in the network.
All Works
| # | Work | Indexed citations |
|---|---|---|
| 1 | 5 | |
| 2 | 3 | |
| 3 | 5 | |
| 4 | 3 | |
| 5 | 11 | |
| 6 | 7 | |
| 7 | 3 | |
| 8 | 2 | |
| 9 | 11 | |
| 10 | 4 | |
| 11 | 2 | |
| 12 | 6 | |
| 13 | 7 | |
| 14 | 7 | |
| 15 | 6 | |
| 16 | 25 | |
| 17 | 2 | |
| 18 | 6 | |
| 19 | 42 | |
| 20 | VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation | 0 |
About Yici Cai
Yici Cai is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Statistics, Probability and Uncertainty, having authored 220 papers that have together received 1.7k indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (142 papers), Low-power high-performance VLSI design (99 papers) and VLSI and Analog Circuit Testing (76 papers). The work is most often cited by research in Hardware and Architecture (826 citations), Electrical and Electronic Engineering (1.5k citations) and Statistics, Probability and Uncertainty (76 citations). Yici Cai has collaborated with scholars based in China, United States and Hong Kong. Frequent co-authors include Xianlong Hong, Qiang Zhou, Qiang Zhou, Sheldon X.-D. Tan, Hailong Yao, Jianlei Yang, Jun Gu, Zuowei Li, Jiang Hu and Chung‐Kuan Cheng. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Circuits and Systems I Regular Papers and IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.