Yuchun Ma

1.1k total citations
93 papers, 758 citations indexed

About

Yuchun Ma is a scholar working on Electrical and Electronic Engineering, Computer Networks and Communications and Hardware and Architecture. According to data from OpenAlex, Yuchun Ma has authored 93 papers receiving a total of 758 indexed citations (citations by other indexed papers that have themselves been cited), including 80 papers in Electrical and Electronic Engineering, 40 papers in Computer Networks and Communications and 39 papers in Hardware and Architecture. Recurrent topics in Yuchun Ma's work include VLSI and FPGA Design Techniques (59 papers), 3D IC and TSV technologies (36 papers) and Interconnection Networks and Systems (34 papers). Yuchun Ma is often cited by papers focused on VLSI and FPGA Design Techniques (59 papers), 3D IC and TSV technologies (36 papers) and Interconnection Networks and Systems (34 papers). Yuchun Ma collaborates with scholars based in China, United States and Hong Kong. Yuchun Ma's co-authors include Xianlong Hong, Sheqin Dong, Yu Wang, Chung‐Kuan Cheng, Jun Gu, Glenn Reinman, Qiang Zhou, Yici Cai, Wayne Luk and Yuan Xie and has published in prestigious journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems and ACM Transactions on Design Automation of Electronic Systems.

In The Last Decade

Yuchun Ma

82 papers receiving 719 citations

Peers — A (Enhanced Table)

Peers by citation overlap · career bar shows stage (early→late) cites · hero ref

Name h Career Trend Papers Cites
Yuchun Ma China 16 629 242 203 82 59 93 758
Ting-Chi Wang Taiwan 16 791 1.3× 466 1.9× 238 1.2× 17 0.2× 75 1.3× 82 881
Charles H.‐P. Wen Taiwan 15 514 0.8× 349 1.4× 299 1.5× 31 0.4× 47 0.8× 103 795
Sergio Cuenca-Asensi Spain 13 388 0.6× 295 1.2× 122 0.6× 39 0.5× 58 1.0× 69 538
Mimi Xie United States 15 438 0.7× 228 0.9× 216 1.1× 92 1.1× 103 1.7× 51 650
Seung Eun Lee South Korea 11 154 0.2× 141 0.6× 172 0.8× 73 0.9× 59 1.0× 70 405
Hailong Yao China 20 974 1.5× 284 1.2× 78 0.4× 36 0.4× 52 0.9× 87 1.1k
Anuj Pathania Singapore 16 418 0.7× 538 2.2× 438 2.2× 120 1.5× 49 0.8× 46 776
Yih-Lang Li Taiwan 17 737 1.2× 502 2.1× 218 1.1× 42 0.5× 50 0.8× 74 849
Tom Burd United States 10 1.1k 1.8× 1.1k 4.7× 627 3.1× 82 1.0× 35 0.6× 21 1.9k
Zhiyuan Yang United States 8 151 0.2× 112 0.5× 94 0.5× 77 0.9× 62 1.1× 30 358

Countries citing papers authored by Yuchun Ma

Since Specialization
Citations

This map shows the geographic impact of Yuchun Ma's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Yuchun Ma with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Yuchun Ma more than expected).

Fields of papers citing papers by Yuchun Ma

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Yuchun Ma. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Yuchun Ma. The network helps show where Yuchun Ma may publish in the future.

Co-authorship network of co-authors of Yuchun Ma

This figure shows the co-authorship network connecting the top 25 collaborators of Yuchun Ma. A scholar is included among the top collaborators of Yuchun Ma based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Yuchun Ma. Yuchun Ma is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

20 of 20 papers shown
1.
2.
Ma, Yuchun, et al.. (2016). Hybrid two-stage HW/SW partitioning algorithm for dynamic partial reconfigurable FPGAs. Journal of Tsinghua University(Science and Technology). 56(3). 1 indexed citations
3.
Zhang, Chao, Yuchun Ma, & Wayne Luk. (2015). HW/SW Partitioning Algorithm Targeting MPSOC with Dynamic Partial Reconfigurable Fabric. 240–241. 2 indexed citations
4.
Liu, Wulong, et al.. (2011). On-chip hybrid power supply system for wireless sensor nodes. Asia and South Pacific Design Automation Conference. 43–48. 3 indexed citations
5.
Chen, Xiaohong, Yu Wang, Yu Cao, Yuchun Ma, & Huazhong Yang. (2011). Variation-Aware Supply Voltage Assignment for Simultaneous Power and Aging Optimization. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 20(11). 2143–2147. 21 indexed citations
6.
Lin, Tao, et al.. (2011). Novel and efficient min cut based voltage assignment in gate level. 7. 1–6. 7 indexed citations
7.
Wang, Kan, Yuchun Ma, Sheqin Dong, et al.. (2011). Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs. 261–266. 7 indexed citations
8.
Li, Li, et al.. (2010). PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization. Asia and South Pacific Design Automation Conference. 769–774.
9.
Liu, Shenghua, Yuchun Ma, Xianlong Hong, & Yu Wang. (2010). Simultaneous slack budgeting and retiming for synchronous circuits optimization. Asia and South Pacific Design Automation Conference. 49–54. 2 indexed citations
10.
Li, Xin, Yuchun Ma, & Xianlong Hong. (2009). A novel thermal optimization flow using incremental floorplanning for 3D ICs. Asia and South Pacific Design Automation Conference. 347–352. 21 indexed citations
11.
Ma, Yuchun, Xin Li, Yu Wang, & Xianlong Hong. (2009). Thermal-Aware Incremental Floorplanning for 3D ICs Based on MILP Formulation. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. E92-A(12). 2979–2989. 2 indexed citations
12.
Li, Xin, Yuchun Ma, & Xianlong Hong. (2009). A novel thermal optimization flow using incremental floorplanning for 3D ICs. 347–352. 17 indexed citations
13.
Xie, Yuan & Yuchun Ma. (2008). Design space exploration for 3D integrated circuits. 2317–2320. 10 indexed citations
14.
Ma, Yuchun, et al.. (2008). Voltage island aware incremental floorplanning algorithm based on MILP formulation. 2264–2267. 1 indexed citations
15.
Dong, Sheqin, et al.. (2007). A Fast 3D-BSG Algorithm for 3D Packing Problem. e83 a. 2044–2047. 8 indexed citations
16.
Ma, Yuchun, Zhuoyuan Li, Xianlong Hong, Jason Cong, & Sheqin Dong. (2006). Cubic Packing with Various Candidates for 3D IC Design. e83 a. 2079–2081. 2 indexed citations
17.
Ma, Yuchun, Xianlong Hong, Sheqin Dong, et al.. (2004). Stairway compaction using corner block list and its applications with rectilinear blocks. ACM Transactions on Design Automation of Electronic Systems. 9(2). 199–211. 3 indexed citations
18.
Ma, Yuchun, Xianlong Hong, Sheqin Dong, et al.. (2002). Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. Asia and South Pacific Design Automation Conference. 387–392. 3 indexed citations
19.
Ma, Yuchun, et al.. (2001). VLSI Floorplanning with Boundary Constraints Using Corner Block List Representation. IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences. 84(11). 2697–2704.
20.
Ma, Yuchun, Xianlong Hong, Sheqin Dong, et al.. (2001). Floorplanning with abutment constraints based on corner block list. Integration. 31(1). 65–77. 5 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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