I.N. Hajj

2.9k total citations
122 papers, 2.0k citations indexed

About

I.N. Hajj is a scholar working on Electrical and Electronic Engineering, Hardware and Architecture and Computational Theory and Mathematics. According to data from OpenAlex, I.N. Hajj has authored 122 papers receiving a total of 2.0k indexed citations (citations by other indexed papers that have themselves been cited), including 106 papers in Electrical and Electronic Engineering, 75 papers in Hardware and Architecture and 20 papers in Computational Theory and Mathematics. Recurrent topics in I.N. Hajj's work include Low-power high-performance VLSI design (79 papers), VLSI and Analog Circuit Testing (56 papers) and VLSI and FPGA Design Techniques (49 papers). I.N. Hajj is often cited by papers focused on Low-power high-performance VLSI design (79 papers), VLSI and Analog Circuit Testing (56 papers) and VLSI and FPGA Design Techniques (49 papers). I.N. Hajj collaborates with scholars based in United States, Canada and Lebanon. I.N. Hajj's co-authors include S. Bobba, Farid N. Najm, Naresh R. Shanbhag, S. Ramprasad, Andreas Veneris, Ping Yang, Constantine D. Polychronopoulos, Nikolaos Bellas, R. Burch and E.S. Kuh and has published in prestigious journals such as Proceedings of the IEEE, IEEE Journal of Solid-State Circuits and Electronics Letters.

In The Last Decade

I.N. Hajj

111 papers receiving 1.9k citations

Peers

I.N. Hajj

EEE

HA

CNC

CTM

BE

Carl Sechen United States

Mark R. Greenstreet Canada

H.J. De Man Belgium

Yici Cai China

Sunil P. Khatri United States

K. Antreich Germany

I. Bolsens Belgium

Hugo De Man Belgium

Xianlong Hong China

Mauro Olivieri Italy

Carl Sechen United States

I.N. Hajj

2.0k ×1.2

EEE

1.4k ×1.1

HA

380 ×1.1

CNC

285 ×1.2

CTM

152 ×1.2

BE

Citations per year, relative to I.N. Hajj I.N. Hajj (= 1×) peers Carl Sechen

Countries citing papers authored by I.N. Hajj

Since Specialization

Citations

This map shows the geographic impact of I.N. Hajj's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by I.N. Hajj with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites I.N. Hajj more than expected).

Fields of papers citing papers by I.N. Hajj

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by I.N. Hajj. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by I.N. Hajj. The network helps show where I.N. Hajj may publish in the future.

Co-authorship network of co-authors of I.N. Hajj

This figure shows the co-authorship network connecting the top 25 collaborators of I.N. Hajj. A scholar is included among the top collaborators of I.N. Hajj based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with I.N. Hajj. I.N. Hajj is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

1.

Saab, D.G., A.T. Yang, & I.N. Hajj. (2003). Delay modeling and timing of bipolar digital circuits. 1. 288–293. 1 indexed citations

2.

Bobba, S. & I.N. Hajj. (2002). Current-mode threshold logic gates. 235–240. 28 indexed citations

3.

Ramprasad, S., Naresh R. Shanbhag, & I.N. Hajj. (2002). Signal coding for low power: fundamental limits and practical realizations. 2. 1–4. 3 indexed citations

4.

Hajj, I.N., et al.. (2002). Fast mixed-mode simulation for accurate MOS bridging fault detection. 1993 IEEE International Symposium on Circuits and Systems. 1503–1506. 6 indexed citations

5.

Hajj, I.N., et al.. (2002). Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits. 456–462. 12 indexed citations

6.

Tian, Yanmei & I.N. Hajj. (2002). Mixed-mode timing simulation for accurate CMOS bridging fault detection. 643–646.

7.

Ramprasad, S., Naresh R. Shanbhag, & I.N. Hajj. (2002). Coding for low-power address and data busses: a source-coding framework and applications. 18–23. 3 indexed citations

8.

Bobba, S., et al.. (2002). Power bus maximum voltage drop in digital VLSI circuits. 263–268. 9 indexed citations

9.

Bobba, S., et al.. (2000). Simulation and optimization of the power distribution network in VLSI circuits. International Conference on Computer Aided Design. 481–486. 47 indexed citations

10.

Ramprasad, S., Naresh R. Shanbhag, & I.N. Hajj. (1999). A coding framework for low-power address and data busses. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 7(2). 212–221. 171 indexed citations

11.

Ramprasad, S., Naresh R. Shanbhag, & I.N. Hajj. (1999). Signal coding for low power: fundamental limits and practical realizations. IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing. 46(7). 923–929. 19 indexed citations

12.

Shanbhag, Naresh R., et al.. (1998). Decorrelating (DECOR) transformations for low-power adaptive filters. 250–255. 5 indexed citations

13.

Hajj, I.N., et al.. (1997). GOLDENGATE: a fast and accurate bridging fault simulator under a hybrid logic/I/sub DDQ/ testing environment. International Conference on Computer Aided Design. 555–561. 4 indexed citations

14.

Shanbhag, Naresh R., et al.. (1997). Achievable bounds on signal transition activity. International Conference on Computer Aided Design. 126–129. 14 indexed citations

15.

Najm, Farid N., et al.. (1995). Power estimation in sequential circuits. 635–640. 64 indexed citations

16.

Hajj, I.N., et al.. (1994). Delay and area optimization for compact placement by gate resizing and relocation. International Conference on Computer Aided Design. 145–148. 7 indexed citations

17.

Stamoulis, Georgios, et al.. (1994). iProbe-d: a hot-carrier and oxide reliability simulator. 3. 274–279. 11 indexed citations

18.

Sapatnekar, Sachin S., et al.. (1993). A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area. International Conference on Computer Aided Design. 220–223. 9 indexed citations

19.

Saleh, R.A., et al.. (1989). Parallel circuit simulation on supercomputers. Proceedings of the IEEE. 77(12). 1915–1931. 54 indexed citations

20.

Saab, D.G., A.T. Yang, & I.N. Hajj. (1988). Delay modeling and timing of bipolar digital circuits. Design Automation Conference. 288–293. 4 indexed citations

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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