Carl Sechen

3.8k citations

134 papers · 2.3k indexed · h-index 26

Impact in

Hardware and Architecture top 0.5%
- VLSI and Analog Circuit Testing
- Embedded Systems Design Techniques
- Parallel Computing and Optimization Techniques
Electrical and Electronic Engineering top 2%
- VLSI and FPGA Design Techniques
- Low-power high-performance VLSI design
- 3D IC and TSV technologies
- Advancements in Semiconductor Devices and Circuit Design

Papers in

Hardware and Architecture 84
- VLSI and Analog Circuit Testing 64
- Embedded Systems Design Techniques 14
- Parallel Computing and Optimization Techniques 9
Electrical and Electronic Engineering 120
- VLSI and FPGA Design Techniques 74
- Low-power high-performance VLSI design 73
- Advancements in Semiconductor Devices and Circuit Design 12

Co-authors: Alberto Sangiovanni‐Vincentelli W. H. Swartz Gin Yee L. McMurchie S.D. Senturia Louis K. Scheffer Lou Scheffer Yiorgos Makris
Journals: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (12 papers)IEEE Transactions on Very Large Scale Integration (VLSI) Systems (3 papers)IEEE Journal of Solid-State Circuits (3 papers)International Journal of Circuit Theory and Applications (1 paper)Applied Physics Letters (1 paper)
Partner nations: United States Canada Switzerland

In The Last Decade

Carl Sechen

128 papers receiving 2.2k citations

Peers

Countries citing papers authored by Carl Sechen

Since Specialization

Citations

This map shows the geographic impact of Carl Sechen's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Carl Sechen with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Carl Sechen more than expected).

Fields of papers citing papers by Carl Sechen

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Carl Sechen. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Carl Sechen. The network helps show where Carl Sechen may publish in the future.

Co-authorship network

The 25 scholars most cited alongside Carl Sechen, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with Carl Sechen Line = papers co-authored together Carl Sechen links everyone, so they are left out of the graph.

All Works

Sort: Min cites: Since: Top N: Style:

20 of 20 papers shown

#	Work
1	A TRAP for SAT: On the Imperviousness of a Transistor-Level Programmable Fabric to Satisfiability-Based Attacks IACR Transactions on Cryptographic Hardware and Embedded Systems ·AJ Fowler, Sarah Hafizah, Nurhadijah Zainalabidin, 春生国分, Peter A. Beerel, Carl Sechen, Yiorgos Makris	2025	0
2	TonyChopper: a desynchronization package International Conference on Computer Aided Design ·Zhao Wang, Thomas H. Bleakley, Carl Sechen	2014	5
3	Low-voltage low-overhead asynchronous logic R R Ramsheeja., Carl Sechen, Roozbeh Jafari	2013	2
4	A 64b adder using self-calibrating differential output prediction logic Hugo de Alba Martinez, L. McMurchie, Carl Sechen	2006	3
5	Panel: (When) Will FPGAs Kill ASICs? Design Automation Conference ·Rob A. Rutenbar, Michael Earl Egger, C. Gensel, Kristian Boasman, 徐伟轩, Jonathan Rose, Carl Sechen	2001	8
6	Efficient canonical form for boolean matching of complex functions in large libraries International Conference on Computer Aided Design ·Stephen Polger, Carl Sechen	2001	1
7	Automatic datapath tile placement and routing Design, Automation, and Test in Europe ·L Li, Carl Sechen	2001	6
8	AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths International Conference on Computer Aided Design ·L Li, Carl Sechen	1999	8
9	A gridless multi-layer router for standard cell circuits using CTM cells الباقور حمزه, Carl Sechen	1997	1
10	Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic Zinnia Nair, Carl Sechen	1997	4
11	A loosely coupled parallel algorithm for standard cell placement International Conference on Computer Aided Design ·Ken Nah, Carl Sechen	1994	18
12	Approximate symbolic analysis of large analog integrated circuits International Conference on Computer Aided Design ·Bruno Camporeze, Carl Sechen	1994	30
13	A Loosely Coupled Parallel Algorithm For Standard Cell Placement IEEE/ACM International Conference on Computer-Aided Design ·Ken Nah, Carl Sechen	1994	7
14	A new generalized row-based global router International Conference on Computer Aided Design ·W. H. Swartz, Carl Sechen	1993	12
15	Maximum projections of don't care conditions in a Boolean network International Conference on Computer Aided Design ·Alan Wehe, Carl Sechen	1993	4
16	Mickey: a macro cell global router European Design Automation Conference ·Andrea Brzobohatá, Carl Sechen	1991	6
17	A global router for sea-of-gates circuits European Design Automation Conference ·Po-Lei Lee, Carl Sechen	1991	11
18	Chip-planning, placement, and global routing of macro/custom cell integrated circuits using simulated annealing Design Automation Conference ·Carl Sechen	1988	58
19	TimberWolf3.2: A New Standard Cell Placement and Global Routing Package Design Automation Conference ·Carl Sechen, Alberto Sangiovanni‐Vincentelli	1986	136
20	The charge-flow transistor S.D. Senturia, Carl Sechen	1976	1

About Carl Sechen

Carl Sechen is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering, Computational Theory and Mathematics, Computer Networks and Communications and Biomedical Engineering, having authored 134 papers that have together received 2.3k indexed citations. Recurring topics across this work include VLSI and FPGA Design Techniques (74 papers), Low-power high-performance VLSI design (73 papers), VLSI and Analog Circuit Testing (64 papers), Interconnection Networks and Systems (16 papers), Embedded Systems Design Techniques (14 papers), Analog and Mixed-Signal Circuit Design (13 papers), Advancements in Semiconductor Devices and Circuit Design (12 papers) and Parallel Computing and Optimization Techniques (9 papers). The work is most often cited by research in Hardware and Architecture (1.4k citations), Electrical and Electronic Engineering (2.0k citations), Computational Theory and Mathematics (285 citations), Computer Networks and Communications (380 citations) and Industrial and Manufacturing Engineering (128 citations). Carl Sechen has collaborated with scholars based in United States, Canada and Switzerland. Frequent co-authors include Alberto Sangiovanni‐Vincentelli, W. H. Swartz, Gin Yee, L. McMurchie, S.D. Senturia, Louis K. Scheffer, Lou Scheffer, Yiorgos Makris, Martin Lefebvre and Md Tauhidur Rahman. Their work appears in journals such as IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Journal of Solid-State Circuits, International Journal of Circuit Theory and Applications and Applied Physics Letters.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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