K. Sasaki

1.4k citations

34 papers · 953 indexed · h-index 14

Electrical and Electronic Engineering top 5%
Hardware and Architecture top 2%
Biomedical Engineering top 10%
Computational Theory and Mathematics top 5%
Computer Networks and Communications top 10%

Co-authors: Y. Nakagome Toshiaki Yamanaka K. Itoh Akihiro Shimizu N. Ohkubo Makoto Suzuki Koichiro Ishibashi H. Toyoshima
Topics: Low-power high-performance VLSI design (24 papers)Semiconductor materials and devices (19 papers)Advancements in Semiconductor Devices and Circuit Design (16 papers)
Cited by: Hardware and Architecture Electrical and Electronic Engineering Computational Theory and Mathematics
Journals: Proceedings of the IEEE IEEE Journal of Solid-State Circuits IEEE Transactions on Electron Devices
Partner nations: Japan United States United Kingdom

In The Last Decade

K. Sasaki

33 papers receiving 844 citations

Peers

Countries citing papers authored by K. Sasaki

Since Specialization

Citations

This map shows the geographic impact of K. Sasaki's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by K. Sasaki with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites K. Sasaki more than expected).

Fields of papers citing papers by K. Sasaki

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by K. Sasaki. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by K. Sasaki. The network helps show where K. Sasaki may publish in the future.

Co-authorship network of co-authors of K. Sasaki

This figure shows the co-authorship network connecting the top 25 collaborators of K. Sasaki. A scholar is included among the top collaborators of K. Sasaki based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with K. Sasaki. K. Sasaki is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Reduction of Torque Ripple in a SRM through Direct Torque Control 2005 ·Journal of the Magnetics Society of Japan ·K. Sasaki,(unknown),Tetsuyou Watanabe,Hai Guo,(unknown)	4
2	Evening Rump Sessions 2005 ·K. Sasaki,K. O’Connor	1
3	UHF High-Power Low-Distortion Transistor Amplifier with High-Dielectric (epsilon/sub r/=39) Substrate 2005 ·Y. Kajiwara,Takashi Noguchi,(unknown),H. Takamizawa,K. Hirakawa,K. Sasaki	1
4	INVESTIGATION OF ACCELERATION PERFORMANCE FEELING ON A ROTARY ENGINE SPORTS CAR WITH DRIVING SIMULATOR. IN: HUMAN FACTORS IN DRIVING, SEATING AND VISION 2003 ·(unknown),(unknown),(unknown),(unknown),K. Sasaki	1
5	A 7 ns 140 mW 1 Mb CMOS SRAM with current sense amplifier 2003 ·K. Sasaki,(unknown),(unknown),(unknown),(unknown),(unknown),(unknown),(unknown),(unknown)	0
6	A 9 ns 1 Mb CMOS SRAM 2003 ·K. Sasaki,(unknown),Koichiro Ishibashi,Toshiaki Yamanaka,N. Hashimoto,Takashi Nishida,K. Shimohigashi,(unknown)	2
7	High-speed, low-voltage design for high-performance static RAMs 2002 ·K. Sasaki	1
8	Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer 1996 ·M. Hiraki,(unknown),Hirotsugu Kojima,(unknown),(unknown),(unknown),K. Sasaki,Kazuhiko Seki	6
9	Advanced TFT SRAM cell technology using a phase-shift lithography 1995 ·IEEE Transactions on Electron Devices ·Toshiaki Yamanaka,Takayuki Hashimoto,Norio Hasegawa,Takeshi Tanaka,Norikazu Hashimoto,Akihiro Shimizu,(unknown),Koichiro Ishibashi,K. Sasaki,Takashi Nishida,Toshiyuki Mine,Eiji Takeda,(unknown)	30
10	Half-swing clocking scheme for 75% power saving in clocking circuitry 1995 ·IEEE Journal of Solid-State Circuits ·H. Kojima,Shigehisa Tanaka,K. Sasaki	46
11	A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits 1995 ·IEEE Journal of Solid-State Circuits ·(unknown),Hiroyoshi Higuchi,(unknown),K. Sasaki,Toshiaki Yamanaka,Y. Nakagome	6
12	A 1.5 ns 32 b CMOS ALU in double pass-transistor logic 1993 ·Makoto Suzuki,N. Ohkubo,Toshiaki Yamanaka,Akihiro Shimizu,K. Sasaki	54
13	A 16-Mb CMOS SRAM with a 2.3- mu m/sup 2/ single-bit-line memory cell 1993 ·IEEE Journal of Solid-State Circuits ·K. Sasaki,Kazuhiro Ueda,(unknown),H. Toyoshima,Koichiro Ishibashi,Toshiaki Yamanaka,Norikazu Hashimoto,(unknown)	9
14	A 1.5-ns 32-b CMOS ALU in double pass-transistor logic 1993 ·IEEE Journal of Solid-State Circuits ·Makoto Suzuki,N. Ohkubo,(unknown),Toshiaki Yamanaka,Akihiro Shimizu,K. Sasaki,Y. Nakagome	152
15	A voltage down converter with submicroampere standby current for low-power static RAMs 1992 ·IEEE Journal of Solid-State Circuits ·Koichiro Ishibashi,K. Sasaki,H. Toyoshima	27
16	A 1.5-V full-swing BiCMOS logic circuit 1992 ·IEEE Journal of Solid-State Circuits ·M. Hiraki,(unknown),Masataka Minami,Kazuki Sato,(unknown),Atsuo Watanabe,Takashi Nishida,K. Sasaki,Kazuhiko Seki	38
17	A 1-V TFT-load SRAM using a two-step word-voltage method 1992 ·IEEE Journal of Solid-State Circuits ·K. Ishibashi,(unknown),(unknown),K. Sasaki	29
18	A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier 1992 ·IEEE Journal of Solid-State Circuits ·K. Sasaki,Koichiro Ishibashi,Kazuhiro Ueda,(unknown),Toshiaki Yamanaka,N. Hashimoto,H. Toyoshima,Fumiaki Kojima,Akihiro Shimizu	46
19	A 1.7-V adjustable I/O interface for low-voltage fast SRAMs 1992 ·IEEE Journal of Solid-State Circuits ·Koichiro Ishibashi,K. Sasaki,Toshiaki Yamanaka,H. Toyoshima,Fumiaki Kojima	1
20	A 20-ns 256 K4 FIFO memory 1988 ·IEEE Journal of Solid-State Circuits* ·Masanori Hashimoto,Michio Nomura,K. Sasaki,(unknown),Hiroshi Fujiwara,(unknown),K. Abe,(unknown),N. Kitagawa	6

About K. Sasaki

K. Sasaki is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computational Theory and Mathematics, having authored 34 papers that have together received 953 indexed citations. Recurring topics across this work include Low-power high-performance VLSI design (24 papers), Semiconductor materials and devices (19 papers) and Advancements in Semiconductor Devices and Circuit Design (16 papers). The work is most often cited by research in Hardware and Architecture (367 citations), Electrical and Electronic Engineering (856 citations) and Computational Theory and Mathematics (113 citations). K. Sasaki has collaborated with scholars based in Japan, United States and United Kingdom. Frequent co-authors include Y. Nakagome, Toshiaki Yamanaka, K. Itoh, Akihiro Shimizu, N. Ohkubo, Makoto Suzuki, Koichiro Ishibashi, H. Toyoshima, H. Kojima and Shigehisa Tanaka. Their work appears in journals such as Proceedings of the IEEE, IEEE Journal of Solid-State Circuits and IEEE Transactions on Electron Devices.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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