William H. Joyner

1.4k citations
27 papers · 824 indexed · h-index 14

Impact in

Papers in

    • VLSI and Analog Circuit Testing 8
    • Embedded Systems Design Techniques 7
    • Software Testing and Debugging Techniques 3
    • Software Reliability and Analysis Research 2

William H. Joyner

26 papers receiving 744 citations

Peers

William H. Joyner
Comparison fields: 5 of 51
  • Hardware and Architecture 496
  • Software 83
  • Computational Theory and Mathematics 269
  • Electrical and Electronic Engineering 452
  • Computer Networks and Communications 119
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Citations per field
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Citations per year

Countries citing papers authored by William H. Joyner

Since Specialization
Citations

This map shows the geographic impact of William H. Joyner's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by William H. Joyner with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites William H. Joyner more than expected).

Fields of papers citing papers by William H. Joyner

Since Specialization
Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by William H. Joyner. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by William H. Joyner. The network helps show where William H. Joyner may publish in the future.

Co-authors

The 25 scholars most cited alongside William H. Joyner, linked wherever they have co-authored with each other. Click a name or a connecting line to browse the papers they share.

Border = papers with William H. Joyner Line = papers co-authored together William H. Joyner links everyone, so they are left out of the graph.

All Works

20 of 20 papers shown
#Work
1 20141
2 20101
3 20090
4 20081
5 200760
6 20061
7 20038
8 200032
9 198612
10 198620
11 198493
12 1981127
13 197927
14
Microprogram verification considered necessary.
197830
15
Using Machine Descriptions in Program Verification.
197810
16 197846
17 19768
18 197647
19 197620
20 19735

About William H. Joyner

William H. Joyner is a scholar working on Hardware and Architecture, Software, Architecture, Computational Theory and Mathematics and Industrial and Manufacturing Engineering, having authored 27 papers that have together received 824 indexed citations. Recurring topics across this work include VLSI and Analog Circuit Testing (8 papers), Embedded Systems Design Techniques (7 papers), VLSI and FPGA Design Techniques (6 papers), Formal Methods in Verification (6 papers), Logic, programming, and type systems (4 papers), Manufacturing Process and Optimization (4 papers), Software Testing and Debugging Techniques (3 papers) and Software Reliability and Analysis Research (2 papers). The work is most often cited by research in Hardware and Architecture (496 citations), Software (83 citations), Computational Theory and Mathematics (269 citations), Electrical and Electronic Engineering (452 citations) and Computer Networks and Communications (119 citations). William H. Joyner has collaborated with scholars based in United States, United Kingdom and France. Frequent co-authors include Daniël Brand, John A. Darringer, Louise Trevillyan, C.L. Berman, Andrew B. Kahng, Y. Zorian, M. Rodgers, William C. Carter, C. Geoffrey Lau and Alex Orailoğlu. Their work appears in journals such as IBM Journal of Research and Development, Computer, IEEE Transactions on Software Engineering, Journal of the ACM and IEEE Transactions on Education.

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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