Paolo Ienne

6.9k total citations · 1 hit paper
240 papers, 4.3k citations indexed

About

Paolo Ienne is a scholar working on Hardware and Architecture, Electrical and Electronic Engineering and Computer Networks and Communications. According to data from OpenAlex, Paolo Ienne has authored 240 papers receiving a total of 4.3k indexed citations (citations by other indexed papers that have themselves been cited), including 181 papers in Hardware and Architecture, 115 papers in Electrical and Electronic Engineering and 95 papers in Computer Networks and Communications. Recurrent topics in Paolo Ienne's work include Embedded Systems Design Techniques (115 papers), Parallel Computing and Optimization Techniques (108 papers) and Interconnection Networks and Systems (73 papers). Paolo Ienne is often cited by papers focused on Embedded Systems Design Techniques (115 papers), Parallel Computing and Optimization Techniques (108 papers) and Interconnection Networks and Systems (73 papers). Paolo Ienne collaborates with scholars based in Switzerland, United States and France. Paolo Ienne's co-authors include Laura Pozzi, Philip Brisk, Ajay Verma, Kubilay Atasu, Yunji Chen, Olivier Temam, Hadi Parandeh-Afshar, Lana Josipović, Zidong Du and Xiaobing Feng and has published in prestigious journals such as IEEE Access, IEEE Transactions on Computers and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

In The Last Decade

Paolo Ienne

230 papers receiving 4.2k citations

Hit Papers

align trajectories

What are hit papers?

Hit papers significantly outperform the citation benchmark for their cohort. A paper qualifies if it has ≥500 total citations, achieves ≥1.5× the top-1% citation threshold for papers in the same subfield and year (this is the minimum needed to enter the top 1%, not the average within it), or reaches the top citation threshold in at least one of its specific research topics.

ShiDianNao

2015 657 citations Zidong Du, Paolo Ienne et al. Infoscience (Ecole Polytechnique Fédérale de Lausanne) profile →

Peers

Countries citing papers authored by Paolo Ienne

Since Specialization

Citations

This map shows the geographic impact of Paolo Ienne's research. It shows the number of citations coming from papers published by authors working in each country. You can also color the map by specialization and compare the number of citations received by Paolo Ienne with the expected number of citations based on a country's size and research output (numbers larger than one mean the country cites Paolo Ienne more than expected).

Fields of papers citing papers by Paolo Ienne

Since Specialization

Physical SciencesHealth SciencesLife SciencesSocial Sciences

This network shows the impact of papers produced by Paolo Ienne. Nodes represent research fields, and links connect fields that are likely to share authors. Colored nodes show fields that tend to cite the papers produced by Paolo Ienne. The network helps show where Paolo Ienne may publish in the future.

Co-authorship network of co-authors of Paolo Ienne

This figure shows the co-authorship network connecting the top 25 collaborators of Paolo Ienne. A scholar is included among the top collaborators of Paolo Ienne based on the total number of citations received by their joint publications. Widths of edges represent the number of papers authors have co-authored together. Node borders signify the number of papers an author published with Paolo Ienne. Paolo Ienne is excluded from the visualization to improve readability, since they are connected to all nodes in the network.

All Works

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20 of 20 papers shown

#	Work	Indexed citations
1	Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits 2023 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·(unknown), (unknown), (unknown), Lana Josipović, Paolo Ienne	7
2	DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis 2021 ·IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ·(unknown), Lana Josipović, George A. Constantinides, Paolo Ienne, John Wickerson	10
3	Evaluating FPGA clusters under wide ranges of design parameters 2017 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·(unknown), Paolo Ienne	15
4	Retraining-based timing error mitigation for hardware neural networks 2015 ·Design, Automation, and Test in Europe ·(unknown), (unknown), Zidong Du, Ying Wang, Huawei Li, Olivier Temam, Paolo Ienne, David Novo, Xiaowei Li, Yunji Chen, Chengyong Wu	13
5	Wear unleveling: improving NAND flash lifetime by balancing page endurance 2014 ·File and Storage Technologies ·(unknown), David Novo, Paolo Ienne	69
6	SketchiLog: sketching combinational circuits 2014 ·Design, Automation, and Test in Europe ·Andrew Becker, David Novo, Paolo Ienne	3
7	An EDA-friendly protection scheme against side-channel attacks 2013 ·Design, Automation, and Test in Europe ·(unknown), (unknown), Francesco Regazzoni, David Novo, Philip Brisk, Paolo Ienne	10
8	Selective flexibility: breaking the rigidity of datapath merging 2012 ·Design, Automation, and Test in Europe ·Mirjana Stojilović, David Novo, Lazar Šaranovac, Philip Brisk, Paolo Ienne	5
9	A high-level synthesis flow for custom instruction set extensions for application-specific processors 2010 ·Asia and South Pacific Design Automation Conference ·(unknown), Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul	14
10	Improved Synthesis of Compressor Trees on FPGAs by a Hybrid and Systematic Design Approach 2010 ·eScholarship (California Digital Library) ·Hadi Parandeh-Afshar, (unknown), (unknown), Paolo Ienne	5
11	Hybrid LZA: a near optimal implementation of the leading zero anticipator 2009 ·Asia and South Pacific Design Automation Conference ·Amit Verma, Ajay Verma, Philip Brisk, Paolo Ienne	4
12	Fast, quasi-optimal, and pipelined instruction-set extensions 2008 ·Asia and South Pacific Design Automation Conference ·Ajay Verma, Philip Brisk, Paolo Ienne	7
13	Automatic synthesis of compressor trees: reevaluating large counters 2007 ·Design, Automation, and Test in Europe ·Ajay Verma, Paolo Ienne	15
14	Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design 2007 ·International Conference on Computer Aided Design ·Philip Brisk, Ajay Verma, Paolo Ienne	6
15	CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis 2005 ·(unknown), Christophe Dubach, Laura Pozzi, Paolo Ienne	10
16	Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management 2005 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Soner Yaldiz, (unknown), Serdar Taşiran, Paolo Ienne, Yusuf Leblebici	3
17	Operating system support for interface virtualisation of reconfigurable coprocessors 2004 ·Design, Automation, and Test in Europe ·(unknown), Ludovic Righetti, Laura Pozzi, Paolo Ienne	11
18	Programming transparency and portable hardware interfacing: towards general-purpose reconfigurable computing 2004 ·(unknown), Laura Pozzi, Paolo Ienne	9
19	Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors 2002 ·Design, Automation, and Test in Europe ·Laura Pozzi, (unknown), Paolo Ienne	18
20	Is There a future for ANN Hardware 1996 ·Infoscience (Ecole Polytechnique Fédérale de Lausanne) ·Joan Cabestany, Paolo Ienne, Juan‐Manuel Torres‐Moreno, Jordi Madrenas	0

Rankless uses publication and citation data sourced from OpenAlex, an open and comprehensive bibliographic database. While OpenAlex provides broad and valuable coverage of the global research landscape, it—like all bibliographic datasets—has inherent limitations. These include incomplete records, variations in author disambiguation, differences in journal indexing, and delays in data updates. As a result, some metrics and network relationships displayed in Rankless may not fully capture the entirety of a scholar's output or impact.

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